Integrated circuit structure

Patent metadata

Field	Value
Publication number	US-10776557-B2
Application number	US-201816205039-A
Country	US
Kind code	B2
Filing date	Nov 29, 2018
Priority date	Sep 28, 2017
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A semiconductor structure includes first and second device regions. The first device region contains an entirety of a first active area of a first logic device, the second device region contains an entirety of a second active area of a second logic device, and the second device region shares a boundary with the first device region. The semiconductor structure also includes a first metal zero pin positioned partially within the first device region, partially within the second device region, and extending across the boundary, and a via contacting the first metal zero pin. A distance from the center of the via to the boundary is less than or equal to a first predetermined distance, and the via is electrically connected to one of the first logic device or the second logic device.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first device region, the first device region containing an entirety of a first active area of a first logic device;
a second device region, the second device region containing an entirety of a second active area of a second logic device, wherein the second device region shares a boundary with the first device region;
a first metal zero pin positioned partially within the first device region, partially within the second device region, and extending across the boundary; and
a via contacting the first metal zero pin, wherein a distance from the center of the via to the boundary is less than or equal to a first predetermined distance based on a metal zero minimum via enclosure length,
wherein the via is electrically connected to one of the first logic device or the second logic device.

2. The semiconductor structure of claim 1 , wherein the first predetermined distance is equal to half a width of the via plus the metal zero minimum via enclosure length.

3. The semiconductor structure of claim 1 , further comprising a second metal zero pin aligned with the first metal zero pin, wherein
the second metal zero pin is positioned entirely within either the first device region or the second device region, and
the first metal zero pin and the second metal zero pin are separated by a second distance greater than a second predetermined distance.

4. The semiconductor structure of claim 1 , further comprising a metal one wire contacting the via.

5. The semiconductor structure of claim 4 , wherein
the via is a first via of a plurality of vias;
the metal one wire is a first metal one wire of a plurality of metal one wires,
wherein
each metal one wire is aligned with a corresponding via,
the plurality of metal one wires includes a second metal one wire overlying the first device region and a third metal one wire overlying the second device region,
the first metal one wire and the second metal one wire have a pitch corresponding to a metal one minimum spacing rule, and
the first metal one wire and the third metal one wire have a pitch corresponding to the metal one minimum spacing rule.

6. The semiconductor structure of claim 4 , wherein the metal one wire overlies the boundary.

7. The semiconductor structure of claim 4 , wherein the first metal zero pin comprises a metal-zero-over-oxide-layer.

8. A semiconductor structure comprising:
a first device region extending from a first power rail to a second power rail, the first device region containing an entirety of a first active area of a first logic device;
a second device region extending from the first power rail to the second power rail, the second device region containing an entirety of a second active area of a second logic device, wherein the first device region and the second device region share a boundary extending from the first power rail to the second power rail;
a first metal zero pin positioned partially within the first device region, partially within the second device region, and extending across the boundary between the first active area and the second active area; and
a via contacting the first metal zero pin, wherein a distance from the center of the via to the boundary is less than or equal to a first predetermined distance based on a metal zero minimum via enclosure length,
wherein the via is electrically connected to one of the first active area or the second active area.

9. The semiconductor structure of claim 8 , wherein the first metal zero pin is configured to electrically connect to the one of the first active area or the second active area.

10. The semiconductor structure of claim 8 , further comprising a second metal zero pin aligned with the first metal zero pin and overlying the other of the first active area or the second active area.

11. The semiconductor structure of claim 10 , wherein at least one of the first metal zero pin or the second metal zero pin comprises a metal-zero-over-oxide-layer.

12. The semiconductor structure of claim 8 , wherein the first metal zero pin overlies the other of the first active area or the second active area.

13. The semiconductor structure of claim 8 , wherein the via overlies the boundary.

14. A semiconductor structure comprising:
a first logic device positioned between a first power rail and a second power rail, the first logic device comprising a first active area;
a second logic device positioned between the first power rail and the second power rail, the second logic device comprising a second active area aligned with the first active area along a first direction parallel to the first power rail and the second power rail;
a metal pin extending in the first direction and overlying one of the first active area or the second active area; and
a plurality of metal wires extending in a second direction perpendicular to the first direction and having a metal wire pitch,
wherein
a first metal wire of the plurality of metal wires overlies the metal pin and is electrically connected to the one of the first active area or the second active area through the metal pin,
a second metal wire of the plurality of metal wires is adjacent to the first metal wire of the plurality of metal wires, overlies the first active area, and is electrically connected to the first logic device, and
a third metal wire of the plurality of metal wires is adjacent to the first metal wire of the plurality of metal wires, overlies the second active area, and is electrically connected to the second logic device.

15. The semiconductor structure of claim 14 , wherein an entirety of a width of the first metal wire of the plurality of metal wires overlies a gap between the first active area and the second active area.

16. The semiconductor structure of claim 14 , further comprising a via between the first metal wire of the plurality of metal wires and the metal pin, the first metal wire of the plurality of metal wires being electrically connected to the one of the first active area or the second active area through the via.

17. The semiconductor structure of claim 14 , further comprising:
a fourth metal wire of the plurality of metal wires adjacent to the second metal wire of the plurality of metal wires, overlying the first active area, and electrically connected to the first logic device; and
a fifth metal wire of the plurality of metal wires adjacent to the third metal wire of the plurality of metal wires, overlying the second active area, and electrically connected to the second logic device.

18. The semiconductor structure of claim 17 , further comprising:
a sixth metal wire of the plurality of metal wires adjacent to the fourth metal wire of the plurality of metal wires, overlying the first active area, and electrically connected to the first logic device; and
a seventh metal wire of the plurality of metal wires adjacent to the fifth metal wire of the plurality of metal wires, overlying the second active area, and electrically connected to the second logic device.

19. The semiconductor structure of claim 14 , wherein the plurality of metal wires is part of a first metal layer of a metal interconnect within the semiconductor structure.

20. The semiconductor structure of claim 14 , wherein
the first active area is a part of a fin field-effect transistor (FinFET) in the first logic device, and
the second active area is a part of a FinFET in the second logic device.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Po-Hsiang
• Chen Sheng-Hsiung
• Chang Fong-Yuan

Classifications

• H10D89/213

  in field-effect devices · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/01 Primary

  Manufacture or treatment · CPC title