On-chip monitor circuit and semiconductor chip

Patent metadata

Field	Value
Publication number	US-10776484-B2
Application number	US-201615543501-A
Country	US
Kind code	B2
Filing date	Jan 12, 2016
Priority date	Jan 13, 2015
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

Provided is an on-chip monitor circuit mounted on a semiconductor chip that is equipped with a security function module for performing a security function process on an input signal and outputting a security function signal, the on-chip monitor circuit comprising a monitor circuit for monitoring signal waveforms of the semiconductor chip, wherein the circuit is provided with a first storage means for storing data that designates a window period in which to perform a test of the semiconductor chip, and a control means for performing control to operate the circuit during the window period, when a prescribed test signal is inputted to the security function module. By using the on-chip monitor circuit in a semiconductor chip of which security is required, security attacks, e.g., a Trojan horse or the like, intended to embed a malicious circuit in the production stage of security function module-equipped semiconductors chips, can be prevented.

First claim

The invention claimed is:

1. An on-chip monitor circuit mounted on a semiconductor chip that is provided with a security function module that performs a security function process on an input signal and outputs a security function signal, the on-chip monitor circuit being provided with a monitor circuit that monitors a signal waveform of the semiconductor chip, wherein the on-chip monitor circuit comprises:
a first storage configured to store data that designates a time window during which the semiconductor chip is tested,
a second storage configured to store a delay code that has been input, and
a controller configured to control such that when a predetermined test signal is input by the security function module the monitor circuit operates during the time window, wherein the controller delays timing of the time window by a delay time corresponding to the delay code.

2. The on-chip monitor circuit as claimed in claim 1 , wherein the controller comprises:
a counter configured to count clock signals and output count value data after receiving a reset signal, and
a comparator configured to compare the count value data and data designating the time window and to cause the monitor circuit to operate when the data match.

3. The on-chip monitor circuit as claimed in claim 1 , wherein the time window is the period of time during which there is the most information leakage in the security function module.

4. The on-chip monitor circuit as claimed in claim 1 , wherein the delay code indicates a delay amount that designates a timing during which there is the most information leakage from the security function module.

5. The on-chip monitor circuit as claimed in claim 1 , wherein the monitor circuit monitors the signal waveform of the substrate potential of the semiconductor chip or the power potential of the security function module.

6. The on-chip monitor circuit as claimed in claim 1 , wherein the controller stops operation of the monitor circuit after testing of the semiconductor chip is finished.

7. The on-chip monitor circuit as claimed in claim 1 , wherein the controller is rendered logically unrewritable by storing at least one predetermined value from the first storage or the second storage after testing of the semiconductor chip is finished.

8. The on-chip monitor circuit as claimed in claim 1 , wherein the security function module is an encryption module.

9. A semiconductor chip provided with a security module that performs a security function process on an input signal and outputs a security function signal, wherein the semiconductor chip comprises:
an on-chip monitor circuit mounted on the semiconductor, the on-ship monitor circuit being provided with a monitor circuit that monitors a signal waveform of the semiconductor chip, wherein the on-chip monitor circuit comprises:
a first storage configured to store data that designates a time window during which the semiconductor chip is test,
a second storage configured to store a delay code that has been input, and
a controller configured to perform control such that when a predetermined test signal is input by the security function module the monitor circuit operates during the time window, wherein the controller delays timing of the time window by a delay time corresponding to the delay code.

10. A semiconductor chip testing system, comprising a semiconductor chip and a testing device that tests the semiconductor chip,
wherein the semiconductor chip is provided with a security module that performs a security function process on an input signal and outputs a security function signal, the semiconductor chip comprising an on-chip monitor circuit mounted on the semiconductor, the on-chip monitor circuit being provided with a monitor circuit that monitors a signal waveform of the semiconductor chip, the on-chip monitor circuit comprising:
a first storage configured to store data that designates a time window during which the semiconductor chip is tested,
a second storage configured to store a delay code that has been input, and
a controller configured to perform control such that when a predetermined test signal is input by the security function module the monitor circuit operates during the time window, wherein the controller delays timing of the time window by a delay time corresponding to the delay code, and

wherein the testing device is provided with
a test signal generator configured to generate a test signal and to deliver said test signal to the semiconductor chip such that a time period of information leakage from the security function module falls within the time window, and
an arbiter configured to judge a security score by quantifying information leakage from the security function module on the basis of the signal waveform from the monitor circuit.

11. A method for testing a semiconductor chip using an on-chip monitor circuit that is mounted on the semiconductor chip that is provided with a security function module that performs a security function process on an input signal and outputs a security function signal, the on-chip monitor circuit being provided with a monitor circuit that monitors a signal waveform of the semiconductor chip, wherein the method comprises:
a step of storing to a first storage data that designates a time window during which the semiconductor chip is tested,
a step of storing a delay code that has been input into a second storage, and
a step of performing control such that when a predetermined test signal is input by the security function module the monitor circuit operates during the time window, and
a step of delaying timing of the time window by a delay time corresponding to the delay code.

12. The method for testing a semiconductor chip as claimed in claim 11 , further comprising:
a step of generating a test signal and delivering said test signal to the semiconductor chip such that a time period of information leakage from the security function module falls within the time window, and
a step of judging a security score by quantifying information leakage from the security function module on the basis of the signal waveform from the monitor circuit.

13. The method for testing a semiconductor chip as claimed in claim 11 , further comprising a step of stopping operation of the monitor circuit after testing of the semiconductor chip is finished.

14. The method for testing a semiconductor chip as claimed in claim 11 , further comprising a step of producing a logically unrewritable state by storing at least one predetermined value from the first storage or the second storage after testing of the semiconductor chip is finished.

15. The method for testing a semiconductor chip as claimed in claim 11 , wherein the security function module is an encryption module.

Assignees

• Univ Kobe Nat Univ Corp
• Telecom Paristech

Inventors

• Nagata Makoto
• Danger Jean-Luc
• Fujimoto Daisuke
• Bhasin Shivam

Classifications

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• G01R31/2884 Primary

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• H04L9/10

  with particular housing, physical features or manual controls · CPC title

• G01R31/31719

  Security aspects, e.g. preventing unauthorised access during test · CPC title