Double data rate interpolating analog to digital converter

Patent metadata

Field	Value
Publication number	US-10771084-B2
Application number	US-201916528005-A
Country	US
Kind code	B2
Filing date	Jul 31, 2019
Priority date	Jan 31, 2017
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.

First claim

What is claimed is:

1. A double data rate comparator device, comprising:
a double data rate comparator core configured to compare a voltage of an input signal (IN) to a reference signal (REF N ) during each of a rising edge and a falling edge in a single clock cycle of a clock input (CLK) to the double data rate comparator core, wherein the double data rate comparator core comprises a p-type metal-oxide-semiconductor (PMOS) differential amplifier stage and an n-type metal-oxide-semiconductor (NMOS) differential amplifier stage connected together in a push-pull configuration; and
a double data rate set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle, wherein the double data rate set-reset flip flop circuit comprises:
a set input (S); and
a reset input (R) connected to respective outputs (P N , M N ) of the double data rate comparator core.

2. The double data rate comparator device of claim 1 , wherein the double data rate comparator core further comprises:
a first node (DM) connecting a first drain of the PMOS differential amplifier stage to a first drain of the NMOS differential amplifier stage; and
a second node (DP) connecting a second drain of the PMOS differential amplifier stage to a second drain of the NMOS differential amplifier stage, wherein a voltage at the first node (DM) and a voltage at the second node (DP) is charged towards a positive supply voltage (VDD) prior to the rising edge in the single clock cycle, wherein the voltage at the first node (DM) and the voltage at the second node (DP) is discharged towards a negative supply voltage (VSS) during the rising edge in the single clock cycle, and wherein the voltage at the first node (DM) and the voltage at the second node (DP) is charged towards the positive supply voltage (VDD) during the falling edge in the single clock cycle.

3. The double data rate comparator device of claim 2 , wherein a plus comparator core output (OUTP) of the double data rate comparator core is produced by a complementary metal-oxide-semiconductor (CMOS) inverter coupled to the first node (DM) and a minus comparator core output (OUTM) of the double data rate comparator core is produced by a second CMOS inverter coupled to the second node (DP), and wherein a timing of the plus comparator core output (OUTP) and the minus comparator core output (OUTM) is proportional to a voltage difference between the input signal (IN) and the reference signal (REF N ).

4. The double data rate comparator device of claim 1 , wherein the double data rate set-reset flip flop circuit comprises:
a first set-reset (SR) latch circuit connected in parallel with a second SR latch circuit;
a third SR latch circuit;
a switching device configured to selectively connect outputs of the first SR latch circuit; and
a controller configured to control the switching device to switch between the outputs of the first SR latch circuit and the outputs of the second SR latch circuit in response to a state of a signal on the set input (S) and a state of a signal on the reset input (R) to the double data rate set-reset flip flop circuit being equal.

5. The double data rate comparator device of claim 4 , wherein a set input and a reset input of the first SR latch circuit are connected to the respective outputs (P N , M N ) of the double data rate comparator core, and wherein a set input and a reset input of the second SR latch circuit are connected to inverted forms of the respective outputs (P N , M N ) of the double data rate comparator core.

6. The double data rate comparator device of claim 4 , wherein the set input of the first SR latch circuit is connected to a set input node (S) of the set-reset circuit, wherein the reset input of the first SR latch circuit is connected to a reset input node (R) of the set-reset circuit, wherein the reset input of the second SR latch circuit is connected to an output of an inverter connected between the set input node (S) and the reset input, wherein the set input of the second SR latch circuit is connected to an output of an inverter connected between the reset input node (R) and the set input, and wherein the switching device is configured to selectively connect a first input of the third SR latch circuit and a second input of the third SR latch circuit to first and second outputs of the first SR latch circuit and the first and second outputs of the second SR latch circuit.

7. The double data rate comparator device of claim 4 , wherein the controller comprises a first input connected to a set (S) input node of the set-reset circuit, a second input connected to a reset (R) node of the set-reset circuit, and an output connected to a switching control input of the switching device.

8. The double data rate comparator device of claim 1 , wherein the double data rate set-reset flip flop circuit comprises:
a first set-reset (SR) latch circuit connected in parallel with a second SR latch circuit;
a third SR latch circuit;
a switching device configured to selectively connect outputs of the second SR latch circuit to respective inputs of the third SR latch circuit; and
a controller configured to control the switching device to switch between the outputs of the first SR latch circuit and the outputs second SR latch circuit in response to a state of a signal on the set input (S) and a state of a signal on the reset input (R) to the set-reset circuit being equal.

9. The double data rate comparator device of claim 1 , wherein the double data rate comparator core further comprises:
a first node (DM) connecting a first drain of the PMOS differential amplifier stage to a first drain of the NMOS differential amplifier stage; and
a second node (DP) connecting a second drain of the PMOS differential amplifier stage to a second drain of the NMOS differential amplifier stage.

10. A radio receiver comprising:
a double data rate comparator device, comprising:
a double data rate comparator core configured to compare a voltage of an input signal (IN) to a reference signal (REF N ) during each of a rising edge and a falling edge in a single clock cycle of a clock input (CLK) to the double data rate comparator core, wherein the double data rate comparator core comprises a p-type metal-oxide-semiconductor (PMOS) differential amplifier stage and a n-type metal-oxide-semiconductor (NMOS) differential amplifier stage connected together in a push-pull configuration; and
a double data rate set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle, wherein the double data rate set-reset flip flop circuit comprises:
a set input (S); and
a reset input (R) connected to respective outputs (P N , M N ) of the double data rate comparator core.

11. The radio receiver of claim 10 , wherein the double data rate comparator core further comprises:
a first node (DM) connecting a first drain of the PMOS differential amplifier stage to a first drain of the NMOS differential amplifier stage; and
a second node (DP) connecting a second drain of the PMOS differential amplifier stage to a second drain of the NMOS differential amplifier stage, wherein a voltage at the first node (DM) and a voltage at the second node (DP) is charged towards a positive supply voltage (VDD) prior to the rising edge in the single clock cycle, wherein the voltage at the first node (DM) and the voltage at the second node (DP) is discharged towards a negative supply voltage (VSS) during the rising edge in the single clock cycle, and wherein the voltage at the first node (DM) and the voltage at the

Assignees

• Huawei Tech Co Ltd

Inventors

• Koli Kimmo

Classifications

• H04B1/16

  Circuits · CPC title

• H03M1/206 Primary

  using a logic interpolation circuit · CPC title

• H03K3/0233

  Bistable circuits · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title