Charge pump circuits for clock and data recovery

Patent metadata

Field	Value
Publication number	US-10771065-B2
Application number	US-201916664666-A
Country	US
Kind code	B2
Filing date	Oct 25, 2019
Priority date	Jul 28, 2017
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.

First claim

What is claimed is:

1. A charge pump device comprising:
a first switch comprises a first output and coupled to a late signal;
a second switch comprises a second output and coupled to an early signal, the second output being directly coupled to the first output;
an output resistor coupled to the first output and the second output and configured to output a charge pump current based at least on the first output and the second output; and
a first resistor coupled to the first switch;
a second resistor coupled to the second switch;
wherein the charge pump current is at a high voltage when the first switch is on.

2. The device of claim 1 further comprising a third switch for providing equalization between the first switch and the second switch.

3. The device of claim 1 wherein the charge pump current is low when the second switch is on.

4. The device of claim 1 further comprises an operational amplifier coupled to the second switch via a first resistor.

5. The device of claim 1 wherein the charge pump current has a magnitude of less than 40 uA.

6. The device of claim 1 wherein the first switch is coupled to a first capacitor, and the second switch is coupled to a second capacitor, the first capacitor and the second capacitor are a matched pair.

7. The device of claim 1 wherein
the first resistor and the second resistor are a matched pair.

8. The device of claim 1 further comprising an input transistor coupled to a digital-to-analog converter.

9. The device of claim 1 wherein the charge pump current is positive when the first switch is closed.

10. The device of claim 1 wherein the charge pump current is negative when the first switch is closed.

11. A clock data recover (CDR) device configured to generate a clock signal based on an input data stream, the device comprising:
a data sampler for sampling the input data stream;
a phase detector configured to generate an early signal and a late signal based on the input data stream;
a charge pump comprising a first switch and a second switch and a third switch, the first switch being coupled to a first differential voltage based on the late signal, the second switch being coupled to a second differential voltage based on the early signal, the charge pump being configured to generate an offset signal for adjusting the clock signal using a charge pump current based on the first differential voltage and the second differential voltage, the third switch being configured to provide equalization between the first switch and the second switch;
a loop filter; and
a voltage-controlled oscillator (VCO).

12. The device of claim 11 further comprising an edge sampler.

13. The device of claim 11 wherein phase detector comprises a bang-bang phase detector.

14. The device of claim 11 wherein the data sampler is coupled to an amplifier.

15. The device of claim 11 wherein the loop filter is configured to generate a loop filter voltage.

16. The device of claim 11 further comprising an output terminal coupled to a de-multiplexer.

17. A charge pump circuit device comprising:
a first transistor configured to generate a first differential voltage based on an input signal, the first transistor comprising a first gate terminal and a first output terminal;
a first resistor and a second resistor coupled to a first output terminal;
an operational amplifier comprising a first input terminal and a second output terminal, the second output terminal being coupled to the first output terminal;
a first switch coupled to the first output terminal, the first switch being turned on by a late signal;
a second transistor comprising a second gate terminal and a third output terminal, the second gate terminal being coupled to the second output terminal;
a third resistor coupled to the third output terminal;
a second switch coupled to the third output terminal, the second switch being turned on by an early signal; and
a fourth resistor coupled to the first switch and the second switch, the fourth resistor being associated with a charge pump current, the charge pump current being at a high voltage when the first switch is on.

18. The device of claim 17 wherein:
the fourth resistor is coupled to a loop filter;
the operational amplifier further comprises a fourth output signal, the fourth output signal being coupled to the loop filter.

19. The device of claim 17 further comprising a third switch coupled directly to the first switch and the second switch, the third switch being configured to provide equalization between the first switch and the second switch.

20. The device of claim 17 wherein the second resistor and the third resistor are a matched pair.

Assignees

• Inphi Corp

Inventors

• Forey Simon
• Mishra Parmanand
• Harwood Michael S
• Nagulapalli Rajasekhar

Classifications

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04L7/0058

  detection of error based on equalizer tap values · CPC title

• H03L7/07

  using several loops, e.g. for redundant clock signal generation · CPC title

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title