Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10770403-B2
Application number	US-201816197764-A
Country	US
Kind code	B2
Filing date	Nov 21, 2018
Priority date	May 4, 2018
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic radiation blocking layer disposed above the semiconductor chip and including a base layer in which a plurality of degassing holes are formed and a porous blocking portion filled in the plurality of degassing holes.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a connection member including an insulating layer and a redistribution layer;
a semiconductor chip disposed on the connection member;
an encapsulant encapsulating the semiconductor chip; and
an electromagnetic radiation blocking layer disposed above the semiconductor chip and including a base layer in which a plurality of degassing holes are formed and a porous blocking portion filled in the plurality of degassing holes.

2. The fan-out semiconductor package of claim 1 , wherein the porous blocking portion has a form in which a plurality of particles are agglomerated.

3. The fan-out semiconductor package of claim 1 , wherein the porous blocking portion is a porous plating layer.

4. The fan-out semiconductor package of claim 1 , wherein the base layer comprises metal thin film.

5. The fan-out semiconductor package of claim 1 , wherein the base layer comprises a Cu plating layer.

6. The fan-out semiconductor package of claim 1 , wherein the electromagnetic radiation blocking layer includes a first region and a second region, and a density of the degassing holes is higher in the first region than in the second region.

7. The fan-out semiconductor package of claim 6 , wherein the second region is disposed in a region corresponding to the semiconductor chip.

8. The fan-out semiconductor package of claim 6 , further comprising a core member including a through-hole in which the semiconductor chip is accommodated and a metal layer covering walls forming the through-hole.

9. The fan-out semiconductor package of claim 8 , wherein the metal layer of the core member and the electromagnetic radiation blocking layer are connected to each other by a conductive via penetrating through the encapsulant.

10. The fan-out semiconductor package of claim 6 , further comprising a plurality of passive components disposed on the connection member.

11. The fan-out semiconductor package of claim 10 , wherein the first region is disposed in a region corresponding to at least some of the plurality of passive components.

12. The fan-out semiconductor package of claim 11 , wherein distances from upper surfaces of at least some of the plurality of passive components to an upper surface of the encapsulant are different from each other, and a density of the degassing holes is higher in a region corresponding to a passive component having a larger distance from an upper surface thereof to the upper surface of the encapsulant among the plurality of passive components, the upper surfaces being surfaces of corresponding components and encapsulant away from the connection member.

13. The fan-out semiconductor package of claim 10 , wherein the plurality of passive components include a capacitor and an inductor, and a density of the degassing holes is higher in a region corresponding to the capacitor than in a region corresponding to the inductor.

14. A fan-out semiconductor package comprising:
a connection member including an insulating layer and a redistribution layer;
a semiconductor chip disposed on the connection member;
an encapsulant encapsulating the semiconductor chip; and
an electromagnetic radiation blocking layer disposed above the semiconductor chip and having a porous structure.

15. The fan-out semiconductor package of claim 14 , wherein the electromagnetic radiation blocking layer has a form in which a plurality of particles are agglomerated.

16. The fan-out semiconductor package of claim 14 , wherein the electromagnetic radiation blocking layer is a porous plating layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Mi Ja
• Kim Han
• Park Seong Chan

Classifications

• H10W42/284

  shielding resins · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title