Line end structures for semiconductor devices

Patent metadata

Field	Value
Publication number	US-10770392-B1
Application number	US-201916393973-A
Country	US
Kind code	B1
Filing date	Apr 25, 2019
Priority date	Apr 25, 2019
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A method of fabricating a semiconductor device structure comprising depositing a layer of material on a dielectric stack and patterning the layer of material to form a hard mask, depositing a metal layer covering the hard mask to form a metal hard mask, forming vias in the dielectric stack using the metal hard mask, removing the metal hard mask, and forming trenches in the dielectric stack using the hard mask, wherein the hard mask and the metal hard mask are used to define a line end structure separating the trenches.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device structure comprising:
depositing a layer of material on a dielectric stack and patterning the layer of material to form a hard mask;
depositing a metal layer covering the hard mask to form a metal hard mask;
forming vias in the dielectric stack using the metal hard mask;
removing the metal hard mask; and
forming trenches in the dielectric stack using the hard mask, wherein the metal hard mask and the hard mask are used to define a line end structure separating the trenches.

2. The method of claim 1 , wherein the metal layer selectively deposits on the hard mask to form a uniform thickness thereon.

3. The method of claim 1 , wherein the metal hard mask forms a lower section of the line end structure with a predetermined width during the forming of the vias.

4. The method of claim 1 , wherein the hard mask forms an upper section of the line end structure with a predetermined width during the forming of the trenches.

5. The method of claim 1 , wherein the hard mask further comprises a metal nitride or a metal oxide.

6. The method of claim 1 , wherein the metal hard mask is formed of cobalt (Co) or ruthenium (Ru).

7. A method of fabricating a semiconductor device structure comprising:
forming a dielectric stack;
depositing a layer of masking material on the dielectric stack and patterning the masking material to form a hard mask;
selectively depositing a metal layer covering the hard mask to form a metal hard mask;
forming two vias in the dielectric stack using the metal hard mask;
removing the metal hard mask; and
forming two trenches in the dielectric stack using the hard mask, wherein the hard mask and the metal hard mask are used to define a line end structure separating the two trenches.

8. The method of claim 7 , wherein the forming of the metal hard mask determines a via center to via center spacing and a line end extension portion in each trench for the semiconductor device structure.

9. The method of claim 7 , wherein the patterning of the layer of masking material determines a length for the line end extension portion during the forming of the trenches for the semiconductor device structure.

10. The method of claim 9 further comprises:
depositing a barrier layer in the trenches and vias; and
depositing a metal layer on the barrier layer to form conductive lines having line end extension portions and interconnect vias.

11. The method of claim 7 , wherein forming the dielectric stack further comprises:
forming an etch stop layer; and
depositing an interlayer dielectric on the etch stop layer; wherein the line end structure is formed in the interlayer dielectric.

12. The method of claim 11 further comprises:
depositing a planarizing mask layer over the metal hard mask;
patterning the planarizing mask layer; and
etching using the patterned planarizing mask layer and the metal hard mask to form the vias.

13. The method of claim 11 , wherein forming the dielectric stack further comprises:
forming a metallization mask layer over the interlayer dielectric; and
forming a plurality of patterning lines in the metallization mask layer, wherein the patterning lines are used for etching the interlayer dielectric to form the trenches for the semiconductor device structure.

14. The method of claim 13 , wherein the hard mask formed from the patterning is perpendicularly aligned with and abridges at least two of the patterning lines of the metallization mask layer.

15. The method of claim 7 , wherein the hard mask further comprises TiN or TiO x , wherein x is a number from 1 to 3.

16. The method of claim 7 , wherein the metal layer further comprises Co or Ru and has a uniform thickness between 2 nm to 10 nm.

17. A semiconductor device structure comprising:
a plurality of conductive lines and interconnect vias formed in a dielectric layer having a patterned line end structure;
the line end structure having an upper and lower sections, wherein the upper section is narrower than the lower section;
a first and second conductive lines separated by the upper section of the line end structure; and
a first and second interconnect vias separated by the lower section of the line end structure, the first and second interconnect vias having a height determined by the lower section.

18. A semiconductor device structure of claim 17 , wherein the lower section of the line end structure having a lateral width that defines line end extension portions of the first and second conductive lines; and
the line end extensions are separated by the upper section of the line end structure.

19. A semiconductor device structure of claim 18 , wherein the line end extension portions extend equally towards each other and have a length in the range of 1 to 8 nm.

20. A semiconductor device structure of claim 17 , wherein the via center to via center spacing is less than 40 nm.

Assignees

• Globalfoundries Inc

Inventors

• Licausi Nicholas V
• Law Shao Beng

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/038

  covering conductive structures (H10W20/037 takes precedence) · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title