Semiconductor device and method of forming the same

US10770299B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10770299-B2
Application numberUS-201916726012-A
CountryUS
Kind codeB2
Filing dateDec 23, 2019
Priority dateApr 26, 2017
Publication dateSep 8, 2020
Grant dateSep 8, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A semiconductor device includes a semiconductor fin and a gate structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction substantially perpendicular to the first direction. The gate structure includes a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a semiconductor fin extending along a first direction above a substrate; and a gate structure extending across the semiconductor fin along a second direction substantially perpendicular to the first direction, the gate structure comprising a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, and a filling metal over and in contact with the chlorine-containing N-work function metal layer. 2. The semiconductor device of claim 1 , wherein the gate structure further comprises a titanium nitride layer below and in contact with the chlorine-containing N-work function metal layer. 3. The semiconductor device of claim 1 , wherein the gate structure further comprises a gate dielectric layer below and spaced from the chlorine-containing N-work function metal layer. 4. The semiconductor device of claim 1 , wherein the filling metal is tungsten. 5. The semiconductor device of claim 1 , wherein the gate structure has a minimal width at a position between topmost and bottommost positions of the gate structure. 6. The semiconductor device of claim 1 , wherein the gate structure has a maximal width at a position between topmost and bottommost positions of the gate structure. 7. The semiconductor device of claim 2 , wherein the titanium nitride layer contains carbon. 8. The semiconductor device of claim 2 , wherein the gate structure further comprises a gate dielectric layer below and in contact with the titanium nitride layer. 9. The semiconductor device of claim 8 , wherein the titanium nitride layer has a thickness less than a thickness of the gate dielectric layer. 10. The semiconductor device of claim 3 , wherein the gate dielectric layer has a thickness greater than a thickness of the chlorine-containing N-work function metal layer. 11. A semiconductor device, comprising: a semiconductor fin protruding above a substrate; an N-type source epitaxy structure and an N-type drain epitaxy structure on the semiconductor fin; and a gate structure over the semiconductor fin, the gate structure comprising a high-k gate dielectric layer and a chlorine-containing N-work function metal layer spaced from the high-k gate dielectric layer and laterally between the N-type source epitaxy structure and the N-type drain epitaxy structure. 12. The semiconductor device of claim 11 , wherein the gate structure further comprises a titanium nitride layer over and in contact with the high-k gate dielectric layer, and laterally between the N-type source epitaxy structure and the N-type drain epitaxy structure. 13. The semiconductor device of claim 11 , wherein the gate structure further comprises a tungsten structure in contact with the chlorine-containing N-work function metal layer. 14. The semiconductor device of claim 12 , wherein the titanium nitride layer contains carbon. 15. A method, comprising: forming a fin extending from a semiconductor substrate; forming a shallow trench isolation (STI) structure laterally surrounding a lower portion of the fin; forming a dummy gate structure across an N-type field effect transistor (NFET) channel region in the fin; forming an N-type source epitaxy structure and an N-type drain epitaxy structure respectively on opposite sides of the NFET channel region; and replacing the dummy gate structure with a replacement gate structure, the replacing comprising forming a titanium nitride (TiN) layer of the replacement gate structure on the NFET channel region, and a chlorine-containing N-work function metal layer of the replacement gate structure over the TiN layer on the NFET channel region. 16. The method of claim 15 , wherein the replacing further comprises forming a tungsten layer of the replacement gate structure in contact with the chlorine-containing N-work function metal layer. 17. The method of claim 15 , wherein the replacing further comprises forming a gate dielectric layer of the replacement gate structure prior to forming the TiN layer. 18. The method of claim 15 , further comprising: forming gate spacers on either side of the dummy gate structure prior to replacing the dummy gate structure with the replacement gate structure, wherein the gate spacers define a gate trench therebetween, and the gate trench has a minimal width at a position between topmost and bottommost positions of the gate trench. 19. The method of claim 15 , further comprising: forming gate spacers on either side of the dummy gate structure prior to replacing the dummy gate structure with the replacement gate structure, wherein the gate spacers define a gate trench therebetween, and the gate trench has a maximal width at a position between topmost and bottommost positions of the gate trench. 20. The method of claim 16 , wherein the replacing further comprises performing a chemical mechanical polish (CMP) process on the tungsten layer.

Assignees

Inventors

Classifications

  • H10P14/43Primary

    Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

  • comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

  • being in source or drain regions, e.g. SiGe source or drain · CPC title

  • H10D64/667Primary

    the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

  • characterised by their lengths or sectional shapes · CPC title

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What does patent US10770299B2 cover?
A semiconductor device includes a semiconductor fin and a gate structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction substantially perpendicular to the first direction. The gate structure includes a chlorine-containing N-work function metal layer wrapping around the semiconductor fin, …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/43. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 08 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).