Antifuse device and method of operating the same

Patent metadata

Field	Value
Publication number	US-10770159-B2
Application number	US-201816027358-A
Country	US
Kind code	B2
Filing date	Jul 4, 2018
Priority date	Aug 16, 2017
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions.

First claim

What is claimed is:

1. An antifuse device, comprising:
a substrate having a plurality of active regions;
a plurality of word lines formed in the substrate and extending along a first direction, each of the active regions being cut by two adjacent word lines and divided into a first doped region and two second doped regions;
a plurality of bit lines formed on the substrate and extending along a second direction, the first doped region of each of the active regions being connected to one of the bit lines through a bit line contact structure disposed on the first doped region;
a plurality of source lines formed on the substrate and extending along the second direction, the second doped regions of the active regions being respectively connected to one of the source lines through a source line contact structure disposed on each of the second doped regions; and
a plurality of capacitors arranged along the second direction and respectively sandwiched between the source line contact structure and one of the source lines.

2. The antifuse device according to claim 1 , wherein the first direction and the second direction are perpendicular.

3. The antifuse device according to claim 1 , wherein the active regions extend along a third direction that is not perpendicular to the first direction.

4. The antifuse device according to claim 1 , wherein the bit lines and the source lines are alternately arranged along the second direction from the top view.

5. The antifuse device according to claim 1 , wherein the second doped regions between adjacent two of the bit lines are connected to the same one of the source lines.

6. The antifuse device according to claim 1 , wherein in the cross-sectional view, the source lines are at a horizontal level higher than the bit lines with respect to a surface of the substrate.

7. The antifuse device according to claim 1 , wherein the bit line contact structure extends along the second direction.

8. The antifuse device according to claim 1 , wherein the capacitors respectively have a bottom metal layer, a top metal layer and an insulting layer sandwiched between the bottom metal layer and the top metal layer.

9. The antifuse device according to claim 8 , wherein the bottom metal layer completely covers a top surface of the source line contact structure and has sidewalls completely aligned with sidewalls of the source line contact structure.

10. The antifuse device according to claim 8 , wherein the top metal layer and the insulating layer are completely overlapped and have completely aligned sidewalls.

11. The antifuse device according to claim 8 , wherein the top metal layer and the insulating layer have a first sidewall flush with a lengthwise sidewall of the source line on the top metal layer and a second sidewall completely covered by the source line on the top metal layer.

12. The antifuse device according to claim 8 , wherein the top metal layer and the insulating layer have a same area that is larger than an area of the bottom metal layer.

13. The antifuse device according to claim 1 , wherein the antifuse device has a 6F 2 layout design.

14. A method of operating an antifuse device, comprising:
providing an antifuse device, comprising:
a plurality of word lines;
a plurality of bit lines;
a plurality of source lines alternately arranged with the bit lines; and
a plurality of antifuse cells respectively comprising a transistor and a capacitor, wherein a gate of the transistor has a turn-on voltage and is connected to one of the word lines, a drain of the transistor is connected to one of the bit lines, and a source of the transistor is connected to the capacitor, wherein the capacitor has a breakdown voltage and is connected between the source of the transistor and one of the source lines, wherein a pair of the antifuse cells having the gates both controlled by an m-word line are respectively connected between an n-source line and an n-bit line and between the n-source line and an (n+1)-bit line, the n-source line being between the n-bit line and the (n+1)-bit line; and

providing a word line control signal to the m-word line, a source line control signal to the n-source line, a first bit line control signal to the n-bit line and a second bit line control signal to the (n+1)-bit line to program or read from the pair of the antifuse cells.

15. The method according to claim 14 , wherein the word line control signal is a first voltage larger than the turn-on voltage.

16. The method according to claim 15 , wherein when programming one of the pair of antifuse cells, the source line control signal is a second voltage, the first bit line control signal is a third voltage, the second bit line control signal is a fourth voltage, wherein the second voltage is larger than the third voltage and the fourth voltage.

17. The method according to claim 16 , wherein when programming the antifuse cell connected between the n-source line and an n-bit line, the second voltage is larger than the third voltage by a difference larger than the breakdown voltage, and the second voltage is larger than the fourth voltage by a difference smaller than the breakdown voltage.

18. The method according to claim 16 , wherein when programming the antifuse cell connected between the n-source line and an (n+1)-bit line, the second voltage is larger than the third voltage by a difference smaller than the breakdown voltage, and the second voltage is larger than the fourth voltage by a difference larger than the breakdown voltage.

19. The method according to claim 15 , wherein when reading from the antifuse cell connected between the n-source line and the n-bit line, the source line control signal is a fifth voltage, the first bit line control signal is a reading signal and the second bit line control signal is electrically floating.

20. The method according to claim 15 , wherein when reading from the antifuse cell that is connected between the n-source line and the (n+1)-bit line, the source line control signal is a fifth voltage, the first bit line control signal is electrically floating and the second bit line control signal is a reading signal.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Huang Tsai-Yu
• Wang Pin-Yao

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/491 Primary

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title