Co-optimization of lithographic and etching processes with complementary post exposure bake by laser annealing

Patent metadata

Field	Value
Publication number	US-10768532-B2
Application number	US-201815980501-A
Country	US
Kind code	B2
Filing date	May 15, 2018
Priority date	May 15, 2018
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A method of co-optimizing lithographic and etching processes for semiconductor fabrication. The method includes determining a first set of locations for a first complementary laser annealing to be performed on. The first complementary laser annealing is performed at the first set of locations on at least a first semiconductor wafer of a plurality of semiconductor wafers. The first complementary laser annealing is performed before or after a first post-exposure baking process for the at least first semiconductor wafer. After an etching process has been performed on at least the first semiconductor wafer, a second set of locations is determined for a second complementary laser annealing to be performed on. The second complementary laser annealing is performed at the second set of locations on at least a second semiconductor wafer of the plurality of semiconductor wafers. The second complementary laser annealing is performed before or after a second post-exposure baking process.

First claim

What is claimed is:

1. A method of co-optimizing lithographic and etching processes for semiconductor fabrication, the method comprising:
determining a first set of locations for a first complementary laser annealing to be performed on at least a first semiconductor wafer of a plurality of semiconductor wafers;
after a first post-exposure baking process has been performed on at least the first semiconductor wafer, performing the first complementary laser annealing at the first set of locations on at least the first semiconductor wafer;
after an etching process has been performed on at least the first semiconductor wafer, determining a second set of locations for a second complementary laser annealing to be performed on at least a second semiconductor wafer of the plurality of semiconductor wafers; and
after a second post-exposure baking process has been performed on at least the second semiconductor wafer, performing the second complementary laser annealing at the second set of locations on at least the second semiconductor wafer.

2. The method of claim 1 , wherein determining the first set of locations and performing the first complementary laser annealing are iteratively performed until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a first uniformity of critical dimension threshold, and
wherein determining the second set of locations and performing the second complementary laser annealing are iteratively performed after the at least first uniformity of critical dimension threshold has been satisfied and until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a second uniformity of critical dimension threshold.

3. The method of claim 1 , wherein determining the first set of locations comprises:
analyzing uniformity of critical dimension for features within a given area of at least a third semiconductor wafer of the plurality of semiconductor wafers after a third post-exposure baking process and prior to an etching process;
determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and
selecting the first set of locations from the given area.

4. The method of claim 3 , wherein the given area comprises:
the third semiconductor as a whole;
a plurality of fields within at least the third semiconductor wafer; or
a single a field within at least the third semiconductor wafer.

5. The method of claim 3 , wherein performing the first complementary laser annealing at the first set of locations of the at least second semiconductor wafer comprises:
adjusting one or more operating parameters of the first complementary laser annealing based on determining the uniformity of critical dimension for the features fails to satisfy the one or more uniformity of critical dimension thresholds.

6. The method of claim 1 , wherein determining the second set of locations comprises:
analyzing uniformity of critical dimension for features within a given area of at least the first semiconductor wafer after the etching process;
determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and
selecting the second set of locations from the given area.

7. The method of claim 6 , wherein the given area comprises:
an entirety of at least the first semiconductor as a whole;
a plurality of fields within at least the first semiconductor wafer; or
a single a field within at least the first semiconductor wafer.

8. The method of claim 6 , wherein performing the second complementary laser annealing at the second set of locations of the second semiconductor wafer comprises:
adjusting one or more operating parameters of the second complementary laser annealing based on determining the uniformity of critical dimension for the features fails to satisfy the one or more uniformity of critical dimension thresholds.

9. A method of co-optimizing lithographic and etching processes for semiconductor fabrication, the method comprising:
determining a first set of locations for first complementary laser annealing to be performed on at least a first semiconductor wafer of a plurality of semiconductor wafers;
prior to a first post-exposure baking process being performed on at least the first semiconductor wafer, performing the first complementary laser annealing at the first set of locations on at least the first semiconductor wafer;
after an etching process has been performed on at least the first semiconductor wafer, determining, a second set of locations for a second complementary laser annealing to be performed on at least a second semiconductor wafer of the plurality of semiconductor wafers; and
prior to a second post-exposure baking process being performed on at least the second semiconductor wafer, performing the second complementary laser annealing at the second set of locations on at least the second semiconductor wafer.

10. The method of claim 9 , wherein determining the first set of locations and performing the first complementary laser annealing are iteratively performed until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a first uniformity of critical dimension threshold, and
wherein determining the second set of locations and performing the second complementary laser annealing are iteratively performed after the at least first uniformity of critical dimension threshold has been satisfied and until a uniformity of critical dimension for features within one or more given areas of at least one semiconductor wafer of the plurality of semiconductor wafers satisfies at least a second uniformity of critical dimension threshold.

11. The method of claim 10 , wherein determining the first set of locations comprises:
analyzing uniformity of critical dimension for features within a given area of at least a third semiconductor wafer after a third post-exposure baking process and prior to an etching process;
determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and
selecting the first set of locations from the given area.

12. The method of claim 11 , wherein the given area comprises:
an entirety at least the third semiconductor as a whole;
a plurality of fields within at least the third semiconductor wafer; or
a single a field within at least the third semiconductor wafer.

13. The method of claim 11 , wherein performing the first complementary laser annealing at the first set of locations of at least the second semiconductor wafer comprises:
adjusting one or more operating parameters of the first complementary laser annealing based on determining the uniformity of critical dimension for the features fails to satisfy the one or more uniformity of critical dimension thresholds.

14. The method of claim 10 , wherein determining the second set of locations comprises:
analyzing uniformity of critical dimension for features within a given area of at least the first semiconductor wafer after the etching process;
determining that the uniformity of critical dimension for the features fails to satisfy one or more uniformity of critical dimension thresholds; and
selecting the second set of locations from the given area.

Assignees

• IBM

Inventors

• Sha Jing
• De Silva Ekmini Anuja
• Felix Nelson
• Dunn Derren

Classifications

• G03F7/168

  Finishing the coated layer, e.g. drying, baking, soaking · CPC title

• G03F7/202

  Masking pattern being obtained by thermal means, e.g. laser ablation · CPC title

• G03F7/70625

  Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness · CPC title

• G03F7/7055 Primary

  Exposure light control in all parts of the microlithographic apparatus, e.g. pulse length control or light interruption · CPC title

• G03F7/40 Primary

  Treatment after imagewise removal, e.g. baking · CPC title