Display panel with spacers and walls for the spacers, manufacturing method thereof and display device

US10768489B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10768489-B2
Application numberUS-201715755985-A
CountryUS
Kind codeB2
Filing dateFeb 16, 2017
Priority dateMay 26, 2016
Publication dateSep 8, 2020
Grant dateSep 8, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of the present disclosure provide a display panel and a manufacturing method thereof, and a display device. The display panel includes a first substrate and a second substrate that are opposite to each other. The display panel further includes a spacer located on the first substrate, and at least two walls located on the second substrate. The at least two walls form a recess region. The spacer corresponds to the recess region. The at least two walls are configured to limit a movement of the spacer. According to the embodiments of the present disclosure, the spacer is effectively prevented from slipping into the display region when the display panel is subjected to an external force.

First claim

Opening claim text (preview).

The invention claimed is: 1. A display panel comprising: a first substrate and a second substrate opposite each other; a spacer located on the first substrate; and at least two walls located on the second substrate, wherein the at least two walls form a recess region, wherein the spacer corresponds to the recess region, and wherein the at least two walls are configured to limit movement of the spacer; wherein the wall comprises: a body layer, which is located on the second substrate and protrudes from the second substrate toward the first substrate; and a buffer layer, which is located on a surface of the body layer facing the first substrate; wherein a surface roughness of the buffer layer is less than that of the body layer; wherein a hardness of the buffer layer is less than that of the body layer; wherein the body layer is formed of a source/drain electrode material and an active layer material; wherein the buffer layer is formed of a photoresist material; wherein the display panel further comprises a bulge located in the recess region of the second substrate and in contact with the spacer; and wherein the bulge is formed of a source/drain electrode material. 2. The display panel according to claim 1 , wherein the first substrate is a color film substrate, and wherein the second substrate is an array substrate. 3. The display panel according to claim 1 , wherein the first substrate comprises an opaque region; and wherein the spacer is located in the opaque region of the first substrate. 4. A method for manufacturing a display panel including a first substrate and a second substrate according to claim 1 , comprising: forming a spacer on the first substrate; and forming at least two walls on the second substrate, wherein the at least two walls form a recess region, wherein the spacer corresponds to the recess region, and wherein the at least two walls are configured to limit a movement of the spacer. 5. The method for manufacturing a display panel according to claim 4 , wherein forming at least two walls on the second substrate comprises: forming a body layer, which is located on the second substrate and protrudes from the second substrate toward the first substrate; and forming a buffer layer, which is located on the surface of the body layer facing the first substrate. 6. The method for manufacturing a display panel according to claim 4 , further comprising forming a bulge, which is located in the recess region of the second substrate and in contact with the spacer. 7. The method for manufacturing a display panel according to claim 6 , wherein the body layer, the buffer layer, and the bulge are formed in the same photolithography process using at least one of a gray scale mask and a halftone mask. 8. The method for manufacturing a display panel according to claim 7 , wherein in a photoresist-removal step in the photolithography process, a photoresist on the body layer is retained to form the buffer layer. 9. A display device comprising a display panel according to claim 1 . 10. The display device according to claim 9 , wherein the wall comprises: a body layer, which is located on the second substrate and protrudes from the second substrate toward the first substrate; and a buffer layer, which is located on a surface of the body layer facing the first substrate. 11. The display device according to claim 10 , wherein a surface roughness of the buffer layer is less than that of the body layer. 12. The display panel according to claim 1 , wherein a slope angle of a side of the buffer layer away from the spacer is less than 45 degrees.

Assignees

Inventors

Classifications

  • Spacers having different sizes · CPC title

  • Patterning using multi-mask exposure · CPC title

  • Spacer materials; Spacer properties · CPC title

  • spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

  • Constructional arrangements; {Manufacturing methods}(G02F1/135, G02F1/136 take precedence) · CPC title

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Frequently asked questions

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What does patent US10768489B2 cover?
Embodiments of the present disclosure provide a display panel and a manufacturing method thereof, and a display device. The display panel includes a first substrate and a second substrate that are opposite to each other. The display panel further includes a spacer located on the first substrate, and at least two walls located on the second substrate. The at least two walls form a recess region.…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/13394. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 08 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).