Semiconductor element and methods for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10766769-B2
Application number	US-201815928275-A
Country	US
Kind code	B2
Filing date	Mar 22, 2018
Priority date	Feb 25, 2015
Publication date	Sep 8, 2020
Grant date	Sep 8, 2020

Abstract

A semiconductor element includes a processed substrate arrangement including a processed semiconductor substrate and a metallization layer arrangement on a main surface of the processed semiconductor substrate. The semiconductor element further includes a passivation layer arranged at an outer border of the processed substrate arrangement.

First claim

What is claimed is:

1. A semiconductor element comprising:
a processed substrate arrangement comprising a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate;
a passivation layer arranged at an outer border of the processed substrate arrangement;
a microelectromechanical system (MEMS) functional element arranged at the processed semiconductor substrate; and
a notch formed in the metallization layer structure,
wherein the passivation layer is deposited such that the MEMS functional element, arranged at the processed semiconductor substrate in the notch, and side wall structures of the notch in the metallization layer structure are covered by the passivation layer, and
wherein the metallization layer structure includes a kerf at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement.

2. The semiconductor element according to claim 1 , wherein the MEMS functional element is a MEMS sensor, a MEMS actuator, or a MEMS transducer.

3. The semiconductor element according to claim 1 , wherein the MEMS functional element is arranged at the processed semiconductor substrate in the die region.

4. The semiconductor element according to claim 3 , wherein the MEMS functional element is released from the metallization layer structure by a notch in the metallization layer structure.

5. The semiconductor element according to claim 4 , wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the notch such that at least a portion of the MEMS functional element is exposed.

6. The semiconductor element according to claim 5 , wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the kerf such that at least a portion of the main surface of processed substrate arrangement at the kerf is exposed.

7. The semiconductor element according to claim 5 , wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the kerf, and at a bottom of the kerf such that the main surface of processed substrate arrangement at the kerf is entirely covered by the passivation layer.

8. The semiconductor element according to claim 1 , wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the kerf such that at least a portion of the main surface of processed substrate arrangement at the kerf is exposed.

9. The semiconductor element according to claim claim 1 , wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the kerf, and at a bottom of the kerf such that the main surface of processed substrate arrangement at the kerf is entirely covered by the passivation layer.

10. The semiconductor element according to claim 1 , wherein the passivation layer comprises an insulator material comprising a silicon nitride material.

11. The semiconductor element according to claim 1 , wherein the processed substrate arrangement comprises a breaking edge at the outer border.

12. A semiconductor element, comprising:
a processed substrate arrangement comprising a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate;
a passivation layer arranged at an outer border of the processed substrate arrangement; and
a microelectromechanical system (MEMS) functional element arranged at the processed semiconductor substrate,
wherein the metallization layer structure includes a kerf at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement,
wherein the MEMS functional element is arranged at the processed semiconductor substrate in the die region,
wherein the MEMS functional element is released from the metallization layer structure by a notch in the metallization layer structure, and
wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the notch, and over a surface of the MEMS functional element such that at least a portion of the MEMS functional element is exposed.

13. The semiconductor element according to claim 12 , wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the kerf such that at least a portion of the main surface of processed substrate arrangement at the kerf is exposed.

14. The semiconductor element according to claim 12 , wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the kerf, and at a bottom of the kerf such that the main surface of processed substrate arrangement at the kerf is entirely covered by the passivation layer.

15. A semiconductor element, comprising
a processed substrate arrangement comprising a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate;
a passivation layer arranged at an outer border of the processed substrate arrangement; and
a microelectromechanical system (MEMS) functional element arranged at the processed semiconductor substrate,
wherein the metallization layer structure includes a kerf at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement,
wherein the MEMS functional element is arranged at the processed semiconductor substrate in the die region,
wherein the MEMS functional element is released from the metallization layer structure by a notch in the metallization layer structure, and
wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the notch, and over a surface of the MEMS functional element such that the entire surface of the MEMS functional element is covered by the passivation layer.

16. The semiconductor element according to claim 15 , wherein the passivation layer is arranged at the outer border of the processed substrate arrangement and at a side wall structure of the kerf such that at least a portion of the main surface of processed substrate arrangement at the kerf is exposed.

17. The semiconductor element according to claim 15 , wherein the passivation layer is arranged at the outer border of the processed substrate arrangement, at a side wall structure of the kerf, and at a bottom of the kerf such that the main surface of processed substrate arrangement at the kerf is entirely covered by the passivation layer.

Assignees

• Infineon Technologies Ag

Inventors

• Bretthauer Christian
• Meinhold Dirk

Classifications

• B81B2207/07

  Interconnects · CPC title

• B81B2207/015

  the micromechanical device and the control or processing electronics being integrated on the same substrate · CPC title

• B81B1/002

  Holes characterised by their shape, in either longitudinal or sectional plane · CPC title

• B81B2201/0264

  Pressure sensors · CPC title

• B81C1/00904 Primary

  Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896 · CPC title