Chip package and method for forming the same

Patent metadata

Field	Value
Publication number	US-9355975-B2
Application number	US-201414339355-A
Country	US
Kind code	B2
Filing date	Jul 23, 2014
Priority date	May 11, 2010
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.

First claim

What is claimed is:

1. A chip package, comprising:
a chip having an upper surface, a lower surface and a sidewall, wherein the chip comprises an insulating layer adjacent to the upper surface and a semiconductor substrate adjacent to the lower surface, and wherein the chip comprises a signal pad region in the insulating layer;
a first recess extending from the upper surface toward the lower surface along the sidewall, wherein a first bottom of the first recess is lower than an interface between the insulating layer and the semiconductor substrate;
at least one second recess extending from the first bottom of the first recess in the semiconductor substrate, wherein the first recess and the at least one second recess further laterally extend along a side of the upper surface, and a length of the first recess in the semiconductor substrate extending along the side is greater than that of the at least one second recess in the semiconductor substrate extending along the side; and
a redistribution layer electrically connected to the signal pad region and extending into the at least one second recess.

2. The chip package as claimed in claim 1 , wherein the first recess extends across an entire length of the side of the upper surface.

3. The chip package as claimed in claim 2 , wherein the first recess further extends along at least a partial length of an adjacent side of the upper surface.

4. The chip package as claimed in claim 3 , wherein the chip package comprises a plurality of second recesses extending along the side and the adjacent side of the upper surface, respectively.

5. The chip package as claimed in claim 2 , wherein the first recess further extends along at least a partial length of two adjacent sides.

6. The chip package as claimed in claim 5 , wherein the chip package comprises a plurality of second recesses extending from the first bottom of the first recess toward the lower surface along the side and at least one of the two adjacent sides of the upper surface, respectively.

7. The chip package as claimed in claim 1 , wherein a depth of the first recess is less than that of the at least one second recess.

8. The chip package as claimed in claim 1 , wherein the first bottom of the first recess has a width that is less than that of a second bottom of the at least one second recess.

9. The chip package as claimed in claim 1 , further comprising an another chip, an interposer or a circuit board disposed under the lower surface and electrically connected to the redistribution layer.

10. A method for forming a chip package, comprising:
providing a wafer having a plurality of chips, wherein each chip has an upper surface and a lower surface, and wherein the chip comprises an insulating layer adjacent to the upper surface and a semiconductor substrate adjacent to the lower surface, and comprises a signal pad region in the insulating layer;
forming a first recess extending from the upper surface toward the lower surface, wherein a first bottom of the first recess is lower than an interface between the insulating layer and the semiconductor substrate;
forming at least one second recess extending from the first bottom of the first recess toward the lower surface in the semiconductor substrate;
forming a redistribution layer electrically connected to the signal pad region and extending into the at least one second recess; and
dicing the wafer to separate the plurality of chips, such that the each chip has a sidewall and the first recess extends along the sidewall, wherein the first recess and the at least one second recess further laterally extend a side of the upper surface, and wherein a length of the first recess in the semiconductor substrate extending along the side is greater than that of the at least one second recess in the semiconductor substrate extending along the side.

11. The method as claimed in claim 10 , wherein the first recess extends across an entire length of the side of the upper surface.

12. The method as claimed in claim 11 , wherein the first recess further extends along at least a partial length of an adjacent side of the upper surface.

13. The method as claimed in claim 12 , wherein the method comprises forming a plurality of second recesses in each chip, wherein the plurality of second recesses extends along the side and the adjacent side of the upper surface, respectively.

14. The method as claimed in claim 11 , wherein the first recess further extends along at least a partial length of two adjacent sides.

15. The method as claimed in claim 14 , wherein the method comprises forming a plurality of second recesses in each chip, wherein the plurality of second recesses extends from the first bottom of the first recess toward the lower surface along the side and at least one of the two adjacent sides of the upper surface, respectively.

16. The method as claimed in claim 10 , wherein a depth of the first recess is less than that of the at least one second recess.

17. The method as claimed in claim 10 , wherein the first bottom of the first recess has a width that is less than that of a second bottom of the at least one second recess.

18. The method as claimed in claim 10 , wherein the method further comprises disposing an another chip, an interposer or a circuit board under the lower surface and electrically connected to the redistribution layer.

Assignees

• Xintec Inc

Inventors

• Ho Yen-Shih
• Liu Tsang-Yu
• Chang Shu-Ming
• Huang Yu-Lung
• Lin Chao-Yen
• Suen Wei-Luen
• Chen Chien-Hui
• Liao Chi-Chang

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title