Dry plasma etch method to pattern mram stack
US-2018019387-A1 · Jan 18, 2018 · US
Self-aligned ion beam etch sputter mask for magnetoresistive random access memory
US10763429B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10763429-B2 |
| Application number | US-201816158791-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 12, 2018 |
| Priority date | Oct 12, 2018 |
| Publication date | Sep 1, 2020 |
| Grant date | Sep 1, 2020 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Embodiments of the present invention are directed to a method for fabricating a magnetoresistive random access memory (MRAM) device. A non-limiting example of the method includes depositing a dielectric layer on a contact arranged on a substrate including a magnetic tunnel junction (MTJ) pillar. The method includes reducing a width of the MTJ pillar. The method further includes depositing an encapsulation layer on the dielectric layer and the MTJ pillar.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating a magnetoresistive random access memory (MRAM) device, the method comprising: depositing a dielectric layer on a contact arranged on a substrate comprising a magnetic tunnel junction (MTJ) pillar; reducing a width of the MTJ pillar; and depositing an encapsulation layer on the dielectric layer and the MTJ pillar; wherein reducing the width of the MTJ pillar causes a portion of the dielectric layer to redeposit onto a vertical sidewall of the MTJ pillar. 2. The method of claim 1 , wherein the MTJ pillar is arranged directly on the contact. 3. The method of claim 1 , wherein the dielectric layer is not deposited on the vertical sidewalls of the MTJ pillar. 4. The method of claim 1 , wherein reducing the width of the MTJ pillar comprises ion beam etching. 5. The method of claim 1 , wherein the dielectric layer and the encapsulation layer comprise different dielectric materials. 6. The method of claim 1 , wherein the dielectric layer and the encapsulation layer comprise the same dielectric materials. 7. A method of fabricating a magnetoresistive random access memory (MRAM) device, the method comprising: depositing, by spin coating, a dielectric layer on a contact arranged on a substrate comprising a magnetic tunnel junction (MTJ) pillar; reducing a width of the MTJ pillar to form a gap between a vertical sidewall of the MTJ pillar and the dielectric layer; and depositing an encapsulation layer on the dielectric layer and the MTJ pillar. 8. The method of claim 7 , wherein the dielectric layer is not deposited on the vertical sidewalls of the MTJ pillar. 9. The method of claim 7 , wherein reducing the width of the MTJ pillar comprises ion beam etching. 10. The method of claim 7 , wherein reducing the width of the MTJ pillar causes a portion of the dielectric layer to redeposit onto a vertical sidewall of the MTJ pillar. 11. The method of claim 7 , wherein the dielectric layer and the encapsulation layer comprise different dielectric materials. 12. The method of claim 7 , wherein the dielectric layer and the encapsulation layer comprise the same dielectric materials.
Assignees
Inventors
Classifications
Materials of the active region · CPC title
- H01L43/12Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US10763429B2 cover?
- Embodiments of the present invention are directed to a method for fabricating a magnetoresistive random access memory (MRAM) device. A non-limiting example of the method includes depositing a dielectric layer on a contact arranged on a substrate including a magnetic tunnel junction (MTJ) pillar. The method includes reducing a width of the MTJ pillar. The method further includes depositing an en…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H01L43/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).