LED display and electronic device having same

Patent metadata

Field	Value
Publication number	US-10763247-B2
Application number	US-201916275607-A
Country	US
Kind code	B2
Filing date	Feb 14, 2019
Priority date	Apr 24, 2018
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A display according to various embodiments may include: a first face oriented in a first direction; a second face oriented in a second direction opposite the first direction; a plurality of pixels disposed in a space between the first face and the second face; and a plurality of pins disposed on the second face and configured to electrically connect the plurality of pixels to an external device. Each of the plurality of pixels may include a plurality of LEDs and a driving circuit. A conductive pattern configured to electrically connect the plurality of LEDs to the driving circuit may be located in the space and a wiring line configured to electrically connect the driving circuit to the plurality of pins may be located in the space.

First claim

What is claimed is:

1. A display comprising:
a first face oriented in a first direction;
a second face oriented in a second direction opposite the first direction;
a plurality of pixels disposed in a space between the first face and the second face; and
a plurality of pins disposed on the second face and configured to electrically connect the plurality of pixels to an external device,
wherein each of the plurality of pixels includes a plurality of LEDs and a driving circuit, the driving circuit is disposed in a first layer including the first face, and the plurality of LEDs are disposed in a second layer disposed on the first layer,
the plurality of LEDs are disposed in the space such that light-emitting portions of the plurality of LEDs face the first face,
a conductive pattern configured to electrically connect the plurality of LEDs to the driving circuit is located in the space, at least a portion of the conductive pattern being located above the plurality of LEDs when viewed from above the second face, and
a wiring line configured to electrically connect the driving circuit to the plurality of pins is located in the space, the wiring line being located above the plurality of LEDs when viewed from above the second face.

2. The display of claim 1 , further comprising:
a third layer including the second face and disposed on the second layer, the third layer including at least a portion of the conductive pattern and the wiring line; and
a via configured to electrically connect the driving circuit to the wiring line, at least a portion of the via being disposed in the second layer.

3. The display of claim 2 , wherein the third layer includes:
a conductive pattern layer including at least a portion of the conductive pattern; and
at least one wiring layer disposed on the conductive pattern layer and including the wiring line.

4. The display of claim 1 , wherein the conductive pattern is formed in the space by a process comprising:
disposing the plurality of LEDs on one face on which the driving circuit is disposed in the first layer;
attaching a film on the one face after the disposing process;
removing a portion of the film such that electrodes of the plurality of LEDs are exposed and a portion of the driving circuit is exposed; and
electroplating the exposed electrodes and the exposed portion of the driving circuit after the portion of the film is removed.

5. The display of claim 1 , wherein the first layer comprises glass.

6. A display comprising:
a first face oriented in a first direction;
a second face oriented in a second direction opposite the first direction;
a plurality of pixels disposed in a space between the first face and the second face; and
a plurality of pins disposed on the second face and configured to electrically connect the plurality of pixels to an external device,
wherein each of the plurality of pixels includes a plurality of LEDs and a driving circuit,
the plurality of LEDs are disposed in the space such that light-emitting portions of the plurality of LEDs face the first face,
a conductive pattern configured to electrically connect the plurality of LEDs to the driving circuit is located in the space, at least a portion of the conductive pattern being located above the plurality of LEDs when viewed from above the second face, and
a wiring line configured to electrically connect the driving circuit to the plurality of pins is located in the space, the wiring line being located above the plurality of LEDs when viewed from above the second face;
a first layer including the first face;
a second layer disposed on the first layer and including the plurality of LEDs and the driving circuit, the driving circuit being a chip type;
a third layer including the second face and disposed on the second layer, the third layer including at least a portion of the conductive pattern and the wiring line; and
a via configured to electrically connect the driving circuit chip to the wiring line, at least a portion of the via being disposed in the second layer.

7. The display of claim 6 , wherein the third layer includes:
a conductive pattern layer including at least a portion of the conductive pattern; and
at least one wiring layer disposed on the conductive pattern layer and including the wiring line.

8. The display of claim 6 , wherein the conductive pattern is formed in the space by a process comprising:
disposing the plurality of LEDs and the driving circuit chip on one face of the first layer;
attaching a film on the one face after the disposing process;
removing a portion of the film such that electrodes of the plurality of LEDs are exposed and a portion of the driving circuit chip is exposed; and
electroplating the exposed electrodes and the exposed portion of the driving circuit after the portion of the film is removed.

9. The display of claim 6 , wherein the first layer comprises glass.

10. An electronic device comprising:
a display driver IC;
a power management device comprising power management circuitry:
the display of claim 1 electrically connected to the display driver IC and to the power management device; and
a processor electrically connected to the display driver IC and to the power management device.

11. A display comprising:
a first face oriented in a first direction;
a second face oriented in a second direction substantially opposite the first direction;
a plurality of pixels disposed in a space between the first face and the second face,
wherein each of the plurality of pixels includes a plurality of LEDs and a driving circuit chip, the driving circuit chip is disposed in a first layer including the first face, and the plurality of LEDs are disposed in a second layer disposed on the first layer,
wherein the plurality of LEDs are disposed in the space such that light-emitting portions of the plurality of LEDs face the first face,
a conductive pattern configured to electrically connect the plurality of LEDs to the driving circuit chip and being located in the space, at least a portion of the conductive pattern being located above the plurality of LEDs when viewed from above the second face,
a wiring line configured to electrically connect the driving circuit chip to the plurality of pins and being located in the space, the wiring line being located above the plurality of LEDs when viewed from above the second face,
the second face is one face of glass,
the wiring line is disposed on another face of the glass, and is connected to a via that passes through the one face and the another face, and
the plurality of pixels is connected to an external device via the via.

12. The display of claim 11 , wherein the conductive pattern, the wiring line, and the via are formed in the space by a process comprising:
removing a portion of the glass through the one face and the another face of the glass;
forming a via in the remaining portion of the glass and forming the conductive pattern and the wiring on the another face of the glass; and
disposing the plurality of LEDs on the another face such that light-emitting portions of the plurality of LEDs face away from the another face.

13. An electronic device comprising:
a display driver IC;
a power management device comprising power management circuitry:
the display of claim 11 electrically connected to the display driver IC and to the power management device; and
a processor electrically connected to the display driver IC and to the power management device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Sangtae
• Park Taesang
• Kang Changsun
• Kim Mijin
• Lee Kyoree

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title