Semiconductor device with a multi-layered encapsulant and associated systems, devices, and methods

Patent metadata

Field	Value
Publication number	US-10763131-B2
Application number	US-201715817000-A
Country	US
Kind code	B2
Filing date	Nov 17, 2017
Priority date	Nov 17, 2017
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces, wherein the prefill material directly contacts peripheral surfaces of the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

First claim

We claim:

1. A semiconductor device, comprising:
a substrate including traces, wherein the traces protrude above a top surface of the substrate;
a prefill material over the substrate and between the traces, wherein:
the prefill material directly contacts peripheral surfaces of the traces,
the prefill material corresponds to a first viscosity level for a manufacturing condition,
the prefill material includes a nonconductive liquid encapsulant;

a die attached over the substrate; and
a wafer-level underfill between the prefill material and the die, the wafer-level underfill corresponding to a second viscosity level for the manufacturing condition;
wherein:
the first viscosity level is lower than the second viscosity level; and
the prefill material includes solder mask with a top surface that is coplanar with or below one or more top surfaces of the traces located between peripheral edges of the die.

2. The semiconductor device of claim 1 wherein the prefill material includes a nonconductive paste (NCP).

3. The semiconductor device of claim 2 wherein the NCP includes a fluxing function or trait.

4. The semiconductor device of claim 2 wherein the NCP has a top surface that is coplanar with or above one or more top surfaces of the traces.

5. The semiconductor device of claim 1 wherein the nonconductive liquid encapsulant has a top surface that is coplanar with or below one or more top surfaces of the traces.

6. The semiconductor device of claim 1 wherein the prefill material directly contacts the wafer-level underfill.

7. The semiconductor device of claim 1 wherein:
the prefill material directly contacts the top surface of the substrate;
the die includes a bottom surface and pillars protruding from the die, wherein the pillars are electrically coupled to the traces; and
the wafer-level underfill directly contacts the bottom surface of the die and the pillars.

8. A method of manufacturing a semiconductor device, comprising:
providing a substrate including traces, wherein the traces protrude above a top surface of the substrate;
forming a prefill material over the substrate and between the traces based on jetting a nonconductive liquid encapsulant between the traces, wherein
the prefill material directly contacts peripheral surfaces of the traces; and
jetting the nonconductive liquid encapsulant includes jetting the nonconductive liquid encapsulant with a top surface thereof coplanar with or below top surfaces of one or more of the traces located between peripheral edges of the die; and
attaching an interim structure to the substrate over the prefill material, wherein the interim structure includes a die and a wafer-level underfill between the die and the prefill material.

9. The method of claim 8 wherein jetting the nonconductive liquid encapsulant includes using a high precision jetting process for controlling a location in jetting the nonconductive liquid encapsulant, a volume of the nonconductive liquid encapsulant at the location, or a combination thereof.

10. The method of claim 9 wherein jetting the nonconductive liquid encapsulant includes keeping the nonconductive liquid encapsulant away from top surfaces of the traces.

11. The method of claim 8 further comprising at least partially curing the nonconductive liquid encapsulant before attaching the interim structure.

12. The method of claim 8 wherein attaching the interim structure includes attaching the interim structure without curing the nonconductive liquid encapsulant.

13. The method of claim 8 further comprising at least partially removing a solder mask from between the traces.

14. The method of claim 13 wherein the solder mask between the traces are coplanar with or below top surfaces of one or more of the traces.

15. The method of claim 8 further comprising assembling the interim structure including:
providing the die including pillars extending from a bottom surface of the die;
forming solder bumps on the pillars opposite the die; and
laminating the wafer-level underfill directly contacting the bottom surface and pillars.

16. The method of claim 15 wherein attaching the interim structure includes reflowing the solder bumps and the wafer-level underfill, wherein the solder bumps directly contact the traces and the pillars and the wafer-level underfill directly contacts the prefill material.

Assignees

• Micron Technology Inc

Inventors

• Luo Shijian
• Hacker Jonathan S

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title