Substrate for semiconductor light emitting device and semiconductor light emitting device, and manufacturing methods thereof
US-2015221824-A1 · Aug 6, 2015 · US
Method for manufacturing restored substrate and method for manufacturing light emitting element
US10763100B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10763100-B2 |
| Application number | US-201715845050-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 18, 2017 |
| Priority date | Dec 22, 2016 |
| Publication date | Sep 1, 2020 |
| Grant date | Sep 1, 2020 |
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Abstract
Official abstract text for this publication.
A method for manufacturing a restored substrate includes: removing a nitride semiconductor layer from a stacked-layer in which the nitride semiconductor layer has been laminated on a substrate; oxidizing material adhering to the substrate to produce an oxide deposit after the removing of the nitride semiconductor layer from the stacked-layer; and removing the oxide deposit from the substrate. A method for manufacturing a light emitting element includes stacking nitride semiconductor layers including an active layer on the restored substrate obtained by the above method.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a restored substrate, comprising: providing a stacked-layer in which a nitride semiconductor layer containing silicon has been stacked on a surface of a sapphire substrate; removing the nitride semiconductor layer from the stacked-layer; after the removing of the nitride semiconductor layer from the stacked-layer, a surface of the substrate is exposed; forming an oxide deposit containing SiO 2 by oxidizing a silicon containing-material adhering to the exposed surface of the substrate, the silicon containing-material being caused by the nitride semiconductor layer; and removing the oxide deposit from the substrate to expose the surface of the substrate. 2. The method according to claim 1 , wherein the removing of the nitride semiconductor layer includes removing the nitride semiconductor layer by using chlorine gas. 3. The method according to claim 2 , wherein the removing of the nitride semiconductor layer includes removing the nitride semiconductor at a temperature of 600 to 800° C. 4. The method according to claim 1 , wherein the oxidizing of the material adhering to the substrate includes oxidizing the material adhering to the substrate by using air. 5. The method according to claim 1 , wherein the removing of the oxide deposit from the substrate includes removing the oxide deposit from the substrate by using a hydrofluoric acid-containing solution. 6. The method according to claim 1 , further comprising washing the substrate by pure water after the removing of the nitride semiconductor layer from the stacked-layer and before the oxidizing of the material adhering to the substrate. 7. The method according to claim 1 , further comprising washing the substrate by pure water after removing the oxide deposit from the substrate. 8. The method according to claim 1 , wherein the substrate has protrusions on the surface on which the nitride semiconductor layer is provided. 9. A method for manufacturing a light emitting element, comprising stacking nitride semiconductor layers including an active layer on the restored substrate obtained by the method according to claim 1 .
Assignees
Inventors
Classifications
In-situ cleaning · CPC title
Nitrides · CPC title
being crystalline insulating materials · CPC title
characterised by treatments done before the formation of the materials · CPC title
- H10P70/40Primary
Cleaning for reclaiming · CPC title
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- What does patent US10763100B2 cover?
- A method for manufacturing a restored substrate includes: removing a nitride semiconductor layer from a stacked-layer in which the nitride semiconductor layer has been laminated on a substrate; oxidizing material adhering to the substrate to produce an oxide deposit after the removing of the nitride semiconductor layer from the stacked-layer; and removing the oxide deposit from the substrate. A…
- Who is the assignee on this patent?
- Nichia Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P70/40. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).