Bus sharing scheme

Patent metadata

Field	Value
Publication number	US-10762019-B2
Application number	US-201715647077-A
Country	US
Kind code	B2
Filing date	Jul 11, 2017
Priority date	Jul 1, 2008
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

First claim

What is claimed is:

1. An integrated circuit comprising:
a plurality of configurable components, the plurality of configurable components comprising:
a first set of configurable analog components, and
a second set of configurable digital components;

a routing fabric coupled to the plurality of configurable components, the routing fabric comprising:
a plurality of first analog switches for connection to the first set of configurable analog components, and
a plurality of second digital switches for connection to the second set of configurable digital components;

a plurality of GPIO pads coupled to the routing fabric, the routing fabric for coupling at least two of the configurable components and at least one of the plurality of GPIO pads; and
a control circuit to define a configuration of the routing fabric.

2. The integrated circuit of claim 1 , wherein the at least two of the configurable components comprises at least one configurable digital component and at least one configurable analog component.

3. The integrated circuit of claim 2 , wherein the at least one digital component and the at least one analog component are programmable.

4. The integrated circuit of claim 1 , further comprising at least one fixed-function component.

5. The integrated circuit of claim 1 , further comprising a central processing unit coupled to the routing fabric.

Assignees

• Cypress Semiconductor Corp

Inventors

• Williams Timothy John
• Wright David G
• Kutz Harold M
• Thiagarajan Eashwar
• Snyder Warren S
• Hastings Mark E

Classifications

• H03K19/1732

  by limitation or reduction of the pin/gate ratio (for data-processing equipment G06F1/22) · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title