Bus sharing scheme

Patent metadata

Field	Value
Publication number	US-9720865-B1
Application number	US-201414540238-A
Country	US
Kind code	B1
Filing date	Nov 13, 2014
Priority date	Jul 1, 2008
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

First claim

What is claimed is:

1. A device, comprising:
an analog section and a digital section;
a plurality of input/output (I/O) pads;
an analog routing system, including a plurality of analog routing lines running through a plurality of analog routing segments, to selectively couple at least a portion of the plurality of I/O pads to the analog section, wherein each of the plurality of I/O pads is selectively coupled to at least one of the plurality of analog routing lines by a first type of switch, wherein the first type of switch is configured to selectively couple at least two of the plurality of I/O pads; and
a digital routing system to selectively couple at least a portion of the plurality of I/O pads to the digital section, wherein the digital routing system comprises a plurality of digital routing lines, wherein at least one of the plurality of I/O pads is coupled to at least one of the plurality of digital routing lines by a second type of switch.

2. The device of claim 1 , wherein first and second analog routing segments of the plurality of analog routing segments are coupled by a plurality of transmission gates along the plurality of analog routing lines, wherein the first and the second analog routing segments share the analog routing lines when the transmission gates are closed, wherein the first and the second analog segments operate separately when the transmission gates are opened.

3. The device of claim 1 , wherein at least one of the plurality of I/O pads is coupled to at least one of the plurality of analog routing lines via the first type of switch.

4. The device of claim 1 , wherein at least one of the plurality of analog routing lines is configured to transmit both analog signals and digital signals.

5. The device of claim 1 , wherein the first type of switch includes at least one transmission gate.

6. The device of claim 1 , wherein the second type of switch includes a logic device.

7. The device of claim 2 , wherein the analog section includes at least a first and a second analog sub-section coupled by at least one of the plurality of transmission gates along at least one of the plurality of analog routing lines, wherein the first type of switch associated with the plurality of I/O pads is opened and the at least one of the plurality of transmission gates is closed to allow direct transmission between the first and the second analog sub-sections.

8. The device of claim 1 , wherein the plurality of analog routing lines include analog bus lines.

9. The device of claim 1 , wherein the plurality of digital routing lines include digital bus lines.

10. A method, comprising:
configuring an analog section of a device to communicate over an analog routing system;
configuring a digital section of the device to communicate over a digital routing system, wherein the digital routing system comprises a plurality of digital routing lines;
connecting a plurality of I/O pads of the device to at least one of a plurality of analog routing lines of the analog routing system via a first plurality of transmission gates;
coupling the plurality of I/O pads of the device to at least one of the plurality of digital routing lines of the digital routing system, wherein at least one of the plurality of I/O pads is coupled to at least one of the plurality of digital routing lines by a second type of switch; and
configuring the first plurality of transmission gates to selectively couple at least two of the plurality of I/O pads to one another.

11. The method of 10 , further comprising:
integrating the analog section and the digital section into the device;
dividing the analog routing system into a plurality of analog routing segments, wherein at least one of the plurality of analog routing lines run through the plurality of analog routing segments;
coupling first and second analog routing segments by a second plurality of transmission gates; and
opening the second plurality of transmission gates to allow the first and the second analog routing segments to operate separately.

12. The method of 10 , further comprising:
configuring the at least one of the plurality of analog routing lines of the analog routing system to carry both analog signals and digital signals.

13. The method of 10 , further comprising:
integrating a controller into the device; and
configuring the controller to dynamically reconfigure the coupling of each of the plurality of I/O pads to the at least one of the plurality of analog routing lines of the analog routing system.

14. The method of 10 , wherein coupling the plurality of I/O pads of the device to the at least one of the plurality of digital routing lines comprises:
configuring a plurality of logic devices along the at least one of the plurality of digital routing lines.

15. The method of 10 , further comprising:
configuring the first plurality of transmission gates to selectively couple at least two of the plurality of analog routing lines to one another.

16. A device, comprising:
an analog section coupled with an analog routing network that is divided into a plurality of analog routing segments;
a plurality of I/O pads selectively coupled to at least one of a plurality of analog routing lines of an analog routing segment of the analog routing network by a first type of switch, wherein the analog routing network is configured to selectively couple at least two of the plurality of I/O pads to one another; and
a digital routing system to selectively couple at least a portion of the plurality of I/O pads to the digital section, wherein the digital routing system comprises a plurality of digital routing lines, wherein at least one of the plurality of I/O pads is coupled to at least one of the plurality of digital routing lines by a second type of switch.

Assignees

• Cypress Semiconductor Corp

Inventors

• Williams Timothy J
• Wright David G
• Kutz Harold
• Thiagarajan Eashwar
• Snyder Warren S
• Hastings Mark E

Classifications

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• H03K19/1732

  by limitation or reduction of the pin/gate ratio (for data-processing equipment G06F1/22) · CPC title