Load switch having a controlled slew rate

Patent metadata

Field	Value
Publication number	US-10756725-B2
Application number	US-201816190493-A
Country	US
Kind code	B2
Filing date	Nov 14, 2018
Priority date	Jun 21, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A load switch circuit implemented on an IC chip includes a first node for coupling to an input voltage, a second node for coupling to an external load, first and second capacitor nodes for coupling to first and second terminals of an external capacitor, and a first PFET coupled between the first node and the second node to control an output voltage to the external load. The load switch circuit also includes a driver circuit having a first NFET that has a drain coupled to the first node and a source coupled to a gate of the first PFET. A slew-rate-control circuit is coupled to a gate of the first NFET and includes the first capacitor node, which is coupled to the gate of the first NFET, and the second capacitor node, which is coupled to the second node.

First claim

What is claimed is:

1. A load switch circuit comprising:
an input voltage node;
an external load node;
a first capacitor node adapted to be coupled to a first terminal of an external capacitor;
a second capacitor node adapted to be coupled to a second terminal of the external capacitor;
a first P-type field effect transistor (PFET) having a source and a drian coupled between the input voltage node and the external load node and having a gate;
a driver circuit including a first N-type field effect transistor (NFET) having a drain coupled to the input voltage node, having a source coupled to the gate of the first PFET, and having a gate; and
a slew-rate-control circuit coupled to the gate of the first NFET, the slew-rate-control circuit including the first capacitor node, which is coupled to the gate of the first NFET, and the second capacitor node, which is coupled to the external load node.

2. The load switch circuit as recited in claim 1 including:
a ground plane node;
the slew-rate-control circuit includes:
a second PFET having a source, a drain, and a gate, the second PFET being coupled in series with a first current sink between the input voltage node and the ground plane node, a node between the drain of the second PFET and the first current sink being coupled to the gate of the first NFET, e the gate of the second PFET being coupled to a power down bar input; and

the driver circuit includes:
a third PFET having a source, a drain, and a gate, the third PFET being coupled between the input voltage node and the gate of the first PFET and a second current sink coupled between the gate of the first PFET and the ground plane node, a gate of the third PFET being coupled to the power down bar input.

3. The load switch circuit as recited in claim 2 in which a first current passed by the first current sink is less than a second current passed by the second current sink.

4. The load switch circuit as recited in claim 3 in which a ratio of the first current to the second current is between 1:10 and 1:1,000.

5. The load switch circuit as recited in claim 3 in which a ratio of the first current to the second current is between 1:20 and 1:100.

6. A load switch circuit comprising:
an input voltage node;
an external load node;
a ground plane node;
a first capacitor node adapted to be coupled to a first terminal of an external capacitor;
a second capacitor node adapted to be couple to a second terminal of the external capacitor;
a first P-type field effect transistor (PFET) having a source, a drain, and a gate, the first PFET being coupled between the input voltage node and the external load node;
a driver circuit including a unity gain buffer having an input voltage terminal coupled to the input voltage node and having a ground terminal coupled to the ground plane node, the unity gain buffer havig an inverting input, a non-inverting input, and an output, the output of the unity gain buffer being coupled to the gate of the first PFET; and
a slew-rate-control circuit coupled to the non-inverting input of the unity gain buffer, the slew-rate-control circuit including the first capacitor node, which is coupled to the non-inverting input of the unity gain buffer, and the second capacitor node, which is coupled to the external load node.

7. The load switch circuit as recited in claim 6 in which the slew-rate-control circuit includes a slew-rate-control element coupled between the non-inverting input to the unity gain buffer and the ground plane node.

8. The load switch circuit as recited in claim 6 in which the slew-rate-control circuit includes a disable switch coupled between the input voltage node and the non-inverting input to the unity gain buffer to enable turning the first PFET on and off.

9. The load switch circuit as recited in claim 8 wherein the disable switch includes a second PFET.

10. The load switch circuit as recited in claim 8 the slew-rate-control circuit includes a current sink.

11. The load switch circuit as recited in claim 8 in which the slew-rate-control circuit includes a resistor.

12. A process of operating a load switch circuit having a first P-type field effect transistor (PFET) having a source and a drain coupled between an input voltage node and an external load node and having a gate, the process comprising:
applying power to the input voltage node and applying a power down signal to a gate of a second PFET and to a gate of a third PFET including:
charging a start capacitor from the input voltage node through the second PFET,
charging the gate of the first PFET from the input voltage node through the third PFET, and
turning off the first PFET; and

applying a power down bar signal to the gate of the second PFET and to the gate of the third PFET including:
discharging a first current from the start capacitor to a ground plane node through a first current sink;
discharging a second current from the gate of the first PFET to the ground plane node through a second current sink; and
turning on the first PFET.

13. The process of claim 12 including charging a larger current through the second PFET than is discharged by the first current sink, and charging a larger current through the third PFET than is discharged by the second current sink.

14. The process of claim 12 including setting a turn on slew rate of the first PFET in response to the first current discharged by the first current sink.

15. The process of claim 12 in which a ratio between the first current and the second current is from 1:10 and 1:1,000.

16. The process of claim 12 in which a ratio between the first current and the second current is from 1:20 to 1:100.

17. A load switch circuit comprising:
an input voltage node;
an external load node;
a first P-type field effect transistor (PFET) having a source coupled to the input voltage node, having a drain coupled to the external load node and having a gate, the first PFET having a Miller capacitance between the gate and the drain;
a driver circuit having a first input coupled to the input voltage node, having a second input separate from the first input, and having an output coupled to the gate of the first PFET; and
a first capacitor node coupled to the second input of the driver circuit and a second capacitor node coupled to the external load node.

18. The load switch of claim 17 including a capacitor having a first terminal coupled to the first capacitor node and a second terminal coupled to the second capacitor node.

Assignees

• Texas Instruments Inc

Inventors

• Jordanger Ricky Dale

Classifications

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K5/04 Primary

  by increasing duration; by decreasing duration · CPC title

• H03K17/166 Primary

  Soft switching · CPC title

• H02H9/001

  limiting speed of change of electric quantities, e.g. soft switching on or off (progressive control of electronic switches for eliminating interferences H03K17/16) · CPC title