Nonvolatile memory comprising variable resistance transistors and method for operating the same

Patent metadata

Field	Value
Publication number	US-10756267-B2
Application number	US-201815950193-A
Country	US
Kind code	B2
Filing date	Apr 11, 2018
Priority date	Apr 11, 2017
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.

First claim

What is claimed is:

1. A nonvolatile memory, comprising:
a first memory unit comprising a first bipolar-variable-resistance transistor and a first control transistor which are electrically connected to each other, wherein the first bipolar-variable-resistance transistor is electrically connected to a word-line selecting driving circuit, the first control transistor is electrically connected to a control-line selecting driving circuit, and the first bipolar-variable-resistance transistor is configured to receive a first current flow from a bit-line selecting driving circuit through the first control transistor when the first control transistor is driven by the control-line selecting driving circuit;
a second memory unit comprising a second bipolar-variable-resistance transistor and a second control transistor which are electrically connected to each other, wherein the second bipolar-variable-resistance transistor is electrically connected to the word-line selecting driving circuit, the second control transistor is electrically connected to the control-line selecting driving circuit, and the second bipolar-variable-resistance transistor is configured to receive a second current flow from the bit-line selecting driving circuit through the second control transistor when the second control transistor is driven by the control-line selecting driving circuit; and
an isolation transistor coupled between the first and second memory units and configured to electrically isolate the first and second memory units from each other, wherein the isolation transistor has a gate terminal, a first terminal and a second terminal, the first terminal is directly coupled to the first bipolar-variable-resistance transistor, and the second terminal is directly coupled to the second bipolar-variable-resistance transistor, the gate terminal has a ground potential or a floating electrical potential such that the isolation transistor is always unconducted, wherein the isolation transistor consists of a single MOSFET.

2. The nonvolatile memory of claim 1 , further comprising:
a fin structure extending along a direction, wherein the first control transistor, the first bipolar-variable-resistance transistor, the isolation transistor, the second bipolar-variable-resistance transistor, and the second control transistor respectively comprise gate structures arranged along the direction on the fin structure.

3. The nonvolatile memory of claim 1 , wherein the isolation transistor comprises a gate structure, the nonvolatile memory further comprises an inter-layer dielectric (ILD) layer covering the gate structure of the isolation transistor, so as to allow the gate terminal of the isolation transistor to have the floating electrical potential.

4. A nonvolatile memory, comprising:
a first memory unit comprising a first bipolar-variable-resistance transistor and a first control transistor which are electrically connected to each other, wherein the first bipolar-variable-resistance transistor is electrically connected to a word-line selecting driving circuit, the first control transistor is electrically connected to a control-line selecting driving circuit, and the first bipolar-variable-resistance transistor is configured to receive a first current flow from a bit-line selecting driving circuit through the first control transistor when the first control transistor is driven by the control-line selecting driving circuit;
a second memory unit comprising a second bipolar-variable-resistance transistor and a second control transistor which are electrically connected to each other, wherein the second bipolar-variable-resistance transistor is electrically connected to the word-line selecting driving circuit, the second control transistor is electrically connected to the control-line selecting driving circuit, and the second bipolar-variable-resistance transistor is configured to receive a second current flow from the bit-line selecting driving circuit through the second control transistor when the second control transistor is driven by the control-line selecting driving circuit;
an isolation transistor arranged between the first and second bipolar-variable-resistance transistors and configured to electrically isolate the first and second memory units from each other, wherein a gate terminal of the isolation transistor has a floating potential such that the isolation transistor is always unconducted, wherein the isolation transistor consists of a single MOSFET; and
a fin structure extending along a direction, wherein the first control transistor, the first bipolar-variable-resistance transistor, the second bipolar-variable-resistance transistor, and the second control transistor respectively comprise gate structures arranged along the direction on the fin structure, and the isolation transistor is within the fin structure.

5. A nonvolatile memory, comprising:
a first bipolar-variable-resistance transistor having a first source/drain (S/D) terminal and a second S/D terminal;
a first control transistor electrically connected between a first bit line and the first S/D terminal of the first bipolar-variable-resistance transistor, wherein the first bipolar-variable-resistance transistor is electrically connected to the first bit line through the first control transistor;
a second bipolar-variable-resistance transistor having a third S/D terminal and a fourth S/D terminal;
a second control transistor electrically connected between a second bit line and the fourth S/D terminal of the second bipolar-variable-resistance transistor, wherein the second bipolar-variable-resistance transistor is electrically connected to the second bit line through the second control transistor; and
an isolation transistor coupled between the second S/D terminal of the first bipolar-variable-resistance transistor and the third S/D terminal of the second bipolar-variable-resistance transistor, wherein the isolation transistor has a first terminal and a second terminal, the first terminal is directly coupled to the second S/D terminal of the first bipolar-variable-resistance transistor, and the second terminal is directly coupled to the third S/D terminal of the second bipolar-variable-resistance transistor,
wherein a portion of the first bipolar-variable-resistance transistor between the first and second S/D terminals and a portion of the second bipolar-variable-resistance transistor between the third and fourth S/D terminals are channel regions,
wherein each of the first bipolar-variable-resistance transistor and the second bipolar-variable-resistance transistor further comprises a gate structure, each gate structure comprises a gate metal layer and a variable-resistance insulator stacking, the variable-resistance insulator stacking is formed between the gate metal layer and the channel regions, and the gate metal layer, the variable-resistance insulator stacking and the channel regions form a metal-insulator-semiconductor (MIS) structure,
wherein the channel regions are semiconductive regions of a fin.

6. The nonvolatile memory of claim 5 , wherein the first and second bit lines are electrically connected to a bit-line selecting driving circuit, the first bipolar-variable-resistance transistor has a first gate terminal, the second bipolar-variable-resistance transistor has a second gate terminal, and the nonvolatile memory further comprises:
a first word line configured to electrically connect the first gate terminal of the first bipolar-variable-resistance transistor with a word-line selecting driving circuit, wherein the resistance of the first bipolar-variable-resistance transistor has equivalent to or more than two stable states by voltage or current which is applied to the first bipolar-variable-resistance transistor by the bit-line selecting driving circuit and the wo

Assignees

• Univ National Chiao Tung

Inventors

• Chung Steve S
• Hsieh E-Ray

Classifications

• G11C13/0026 Primary

  Bit-line or column circuits · CPC title

• H10D48/366

  Multistable devices; Devices having two or more distinct operating states · CPC title

• G11C11/5685

  using storage elements comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/15

  Current-voltage curve · CPC title