NAND type variable resistance random access memory and methods

Patent metadata

Field	Value
Publication number	US-9548398-B2
Application number	US-201514807899-A
Country	US
Kind code	B2
Filing date	Jul 24, 2015
Priority date	Jul 28, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A high density NAND-type nonvolatile resistance random access storage circuit and its operations are shown herein . A unit memory cell of the circuit includes a field effect transistor (FET) with a resistance changeable component connected to its gate electrode. The field effect transistor is an n-channel field effect transistor or a p-channel field effect transistor. By applying the voltage or current between the top electrode of the resistive random access component and the FET drain or source electrode, more than two stable states can be maintained such that these states can be drawn from the FET drain or source terminal. The NAND circuit includes the above unit cell as a center to form a multi-bit memory. The circuit consists of multi-bit memories connected in series, has a NAND logic gate function, and forms output of this NAND circuit which can be drawn in a form of series output.

First claim

What is claimed is:

1. A non-volatile resistance random access storage circuit comprising a plurality of memory units, wherein each of the memory units comprises:
a field effect transistor comprising a gate electrode, a source electrode, a drain electrode, and a channel between the gate electrode, the source electrode, and the drain electrode;
a resistance changeable component comprising:
a first electrode or interconnect electrically connected to the gate electrode; and
a second electrode or interconnect electrically connected to a conducting electrode;
wherein the resistance changeable component is formed by laminating at least one oxide layer onto at least one first metal layer, and then laminating at least one second metal layer onto the oxide layer,
wherein the resistance, conductivity or conducting current of the resistance changeable component has equivalent to or more than two stable states by voltage or current sources applied between the first electrode or interconnect and the second electrode or interconnect of the resistance changeable component;
wherein the first electrode or interconnect of the resistance changeable component and the gate electrode of the field effect transistor are in different layers and formed by different materials.

2. The non-volatile resistance random access storage circuit of claim 1 , further comprising:
a word line extended from a word selecting driving circuit used for control the memory unit; wherein the resistance changeable component is arranged at any position of the word line.

3. The non-volatile resistance random access storage circuit of claim 1 , wherein the source electrode of each memory unit is coupled to the drain electrode of an adjacent memory unit in series to form a memory page and a plurality of memory page in parallel to form a memory block, and the non-volatile resistance random access storage circuit further comprises:
a plurality of word lines electrically connected to a word selecting driving circuit;
a plurality of bit lines electrically connected to a bit driving circuit;
a first control transistor comprising a gate terminal, a first terminal and a second terminal, wherein the gate terminal is electrically connected to a bit-line selecting driving circuit through a bit addressing tine, the first terminal is electrically connected to the front end of the memory page, and the second terminal is electrically connected to one of the bit lines; and
a second control transistor comprising a gate terminal, a first terminal and a second terminal, wherein the gate terminal is electrically connected to ,a ground-line selecting driving circuit through a ground line, the first terminal is electrically connected to the back end of the memory page, and the second terminal is electrically connected to a source bias;
wherein the second terminals of the resistance changeable components in the memory block are electrically connected to one of the word lines.

4. The non-volatile resistance random access storage circuit of claim 3 , wherein two adjacent memory blocks are connected in series through a common source bias.

5. A non-volatile resistance random access storage circuit, comprising:
a field effect transistor comprising a gate electrode;
a plurality of resistance changeable components, each comprising:
a first terminal electrically connected to the gate electrode; and
a second terminal electrically connected to a corresponding conducting electrode;
wherein the resistance changeable component is formed by laminating at least one oxide layer onto at least one first metal layer, and then laminating at least one second metal layer onto the oxide layer, wherein the first terminal of the resistance changeable component and the gate electrode of the field effect transistor are in different layers and formed by different materials;
wherein the resistance, conductivity or conducting current of the resistance changeable component has equivalent to or more than two stable states according to a voltage difference or a current source applied between the first terminal and the second terminal of the resistance changeable component,
when a voltage source or a current source is applied to the corresponding conducting electrode, the voltage source makes a region of the transistor be conducted partially, and a memory unit is formed by the region and the resistance changeable component controlled by the conducting electrode.

6. A method for controlling a non-volatile resistance random access storage circuit, wherein the non-volatile resistance random access storage circuit comprises a plurality of memory units connected in series to form a memory page and a plurality of memory page in parallel to form a memory block, each of the memory units comprises a field effect transistor and a resistance changeable component, and the resistance changeable component is formed by laminating at least one oxide layer onto the at least one first metal layer, and then laminating at least one second metal layer onto the oxide layer, wherein the field effect transistor comprises a gate electrode, a source electrode, a drain electrode, and a channel between the gate electrode, the source electrode, and the drain electrode, and the resistance changeable component comprises a first terminal electrically connected to the gate electrode and a second terminal electrically connected to a conducting electrode, and the method comprises;
applying a fixed bias to the field effect transistor of the memory units before any operation is performed to the memory units, and measuring a conducting current as a reference current value;
performing a resetting operation to set the memory units of the memory block in a first, state, and
performing a setting operation to set the selected memory units of the memory block in a second state;
wherein during the resetting operation and the setting operation, bias Voltages with two different polarities are applied on corresponding word lines.

7. The method of claim 6 , wherein the resetting operation comprises:
Selecting the memory block through a bit-line selecting driving circuit and a ground-line selecting driving circuit, such that a first control transistor and a second control transistor connected to the memory block are conducted;
connecting a corresponding bit line and a corresponding source bias to the ground, and
applying a first voltage source or current source to the memory units of the memory page, such that the state of the resistance changeable components of the memory units connected to the word lines is set into a first state.

8. The method of claim 6 , wherein the setting operation comprises:
conducting the first control transistor of the memory page through the bit-line selecting driving circuit;
turning off the second control transistor of the memory page through the ground-line selecting driving circuit;
selecting a target memory unit from the memory block through the word selecting driving circuit, and applying a second voltage source or current source to a corresponding word line to change the state of the resistance changeable component of the selected memory units from the first state into a second state, and
applying a third voltage source or current source to the unselected word lines such that the transistors of the unselected memory units are conducted, and thus the resistance changeable components of the unselected memory units maintain the original state.

9. The method of claim 6 , wherein the setting operation comprises:
selecting the memory page through the bit-line selecting driving circuit, and applying a fourth voltage source or current source such that the fourth source is divided into the selected memory units through the unselecte

Assignees

• Univ Nat Chiao Tung

Inventors

• Chung Steve S
• Hsieh E-Ray

Classifications

• H01L27/2463

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• H01L45/1233

  Electricity · mapped topic

• H01L27/2436

  Electricity · mapped topic