Warpage control of semiconductor die

Patent metadata

Field	Value
Publication number	US-10755995-B2
Application number	US-201916402042-A
Country	US
Kind code	B2
Filing date	May 2, 2019
Priority date	Jun 28, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

First claim

What is claimed is:

1. A method, comprising:
forming a bottom passivation layer on a dielectric layer over a semiconductor substrate;
forming a first opening in the bottom passivation layer to expose a portion of the dielectric layer;
forming a metal pad in the first opening;
forming a first oxide-based passivation layer over the metal pad; and
forming a second oxide-based passivation layer over the first oxide-based passivation layer, the second oxide-based passivation layer having a hardness less than a hardness of the first oxide-based passivation layer.

2. The method of claim 1 , further comprising forming a third oxide-based passivation layer over the metal pad prior to forming the first oxide-based passivation layer.

3. The method of claim 2 , wherein the first and second oxide-based passivation layers are formed using different chemical vapor deposition processes.

4. The method of claim 2 , wherein the first and third oxide-based passivation layers are formed using different chemical vapor deposition processes.

5. The method of claim 2 , wherein the second and third oxide-based passivation layers are formed using a same chemical vapor deposition process.

6. The method of claim 2 , wherein the first oxide-based passivation layer is formed using a high density plasma chemical vapor deposition (HDPCVD).

7. The method of claim 2 , wherein the second and third oxide-based passivation layers are formed using plasma enhanced chemical vapor deposition (PECVD).

8. The method of claim 1 , further comprising:
removing portions of the first and second oxide-based passivation layers to expose the metal pad;
forming a post passivation interconnect (PPI) layer on the metal pad;
forming a buffer layer over the PPI layer;
forming a second opening in the buffer layer;
forming an under bump metallurgy (UBM) layer in the second opening of the buffer layer and in contact with the PPI layer; and
forming a solder ball on the UBM layer.

9. A method, comprising:
forming a bottom passivation layer on a dielectric layer over a semiconductor substrate;
forming a first opening in the bottom passivation layer to expose a portion of the dielectric layer;
forming a metal pad in the first opening and over the bottom passivation layer;
depositing a first oxide-based passivation layer over the metal pad at a first deposition rate; and
depositing a second oxide-based passivation layer over the first oxide-based passivation layer at a second deposition rate faster than the first deposition rate.

10. The method of claim 9 , wherein depositing the second oxide-based passivation layer is performed such that the second oxide-based passivation layer has a thickness less than a thickness of the first oxide-based passivation layer.

11. The method of claim 9 , further comprising:
prior to depositing the first oxide-based passivation layer, depositing a third oxide-based passivation layer over the metal pad at a third deposition rate faster than the first deposition rate.

12. The method of claim 11 , wherein depositing the first oxide-based passivation layer is performed such that a thickness of the first oxide-based passivation layer is greater than a thickness of the third oxide-based passivation layer.

13. The method of claim 11 , wherein depositing the second and third oxide-based passivation layers is performed by using silane and N 2 O as precursors.

14. The method of claim 9 , wherein depositing the first oxide-based passivation layer is performed using silane and O 2 as precursors.

15. The method of claim 9 , further comprising:
forming a nitride-based passivation layer over the second oxide-based passivation layer.

16. A semiconductor die, comprising:
a semiconductor substrate;
a dielectric layer over the semiconductor substrate;
a metal structure in the dielectric layer;
a first metal pad over the metal structure;
a first oxide-based passivation layer over the first metal pad;
a second oxide-based passivation layer over the first oxide-based passivation layer and having a hardness less than a hardness of the first oxide-based passivation layer; and
a bump electrically connected to the first metal pad.

17. The semiconductor die of claim 16 , further comprising a nitride-based passivation layer over the second oxide-based passivation layer.

18. The semiconductor die of claim 16 , wherein a thickness of the first oxide-based passivation layer is greater than a thickness of the second oxide-based passivation layer.

19. The semiconductor die of claim 17 , further comprising:
a third oxide-based passivation layer between the first metal pad and the first oxide-based passivation layer and having a hardness less than the hardness of the first oxide-based passivation layer.

20. The semiconductor die of claim 16 , further comprising:
a second metal pad under the first oxide-based passivation layer and separated from the first metal pad, the second metal pad having a bottom higher than a bottom of the first metal pad.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Yun-Ting
• Lin Yi-An
• Chang Ching-Chuan
• Kuo Po-Chang

Classifications

• H10P14/6682

  the compound being a silane, e.g. disilane, methylsilane or chlorosilane · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title