Vertical transistor having a silicided bottom and method for fabricating thereof

Patent metadata

Field	Value
Publication number	US-10755937-B2
Application number	US-201815918741-A
Country	US
Kind code	B2
Filing date	Mar 12, 2018
Priority date	Apr 7, 2017
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

A method of manufacturing a semiconductor device includes providing a substrate structure including a substrate and a semiconductor column vertically protruding from the substrate, sequentially forming a first protective layer and a second protective layer on the substrate, etching a portion of the second protective layer to expose a portion of the first protective layer on the substrate and a portion of the first protective layer on an upper surface of the semiconductor column, removing the exposed portion of the first protective layer on the substrate to expose a lower portion of the semiconductor column, removing a remaining portion of the second protective layer, and forming a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column. The first contact material layer in contact with the lower portion of the semiconductor column does not increase the source series resistance.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a semiconductor column vertically protruding from the substrate;
a first contact material layer directly on the substrate and in contact with a lower portion of the semiconductor column, the first contact material layer having a recess adjacent to the semiconductor column.

2. The semiconductor device of claim 1 , further comprising:
a first insulating material layer on the first contact material layer;
a gate dielectric material layer on a middle portion of the semiconductor column and on the first insulating material layer exposing an upper portion of the semiconductor column;
a gate material layer on the gate dielectric material layer;
a second insulating material layer on the gate material layer, the second insulating material layer having an upper surface lower than an upper surface of the semiconductor column; and
a second contact material layer on the upper portion of the semiconductor column.

3. The semiconductor device of claim 2 , further comprising:
a first contact extending to the first contact material layer;
a second contact extending to the gate material layer; and
a third contact in contact with the second contact material layer.

4. The semiconductor device of claim 2 , wherein the second contact material layer comprises tungsten, nickel, cobalt, titanium, or platinum.

5. The semiconductor device of claim 1 , wherein the semiconductor column is a nanowire.

6. The semiconductor device of claim 1 , wherein the semiconductor column comprises an array of semiconductor pillars.

7. The semiconductor device of claim 1 , wherein the semiconductor column comprises silicon.

8. The semiconductor device of claim 1 , wherein the first contact material layer comprises tungsten, nickel, cobalt, titanium, or platinum.

9. A semiconductor device, comprising:
a substrate;
a semiconductor column vertically protruding from the substrate;
a gate dielectric material layer on a middle portion of the semiconductor column exposing an upper portion and a lower portion of the semiconductor column;
a first contact material layer on the substrate and in contact with the lower portion of the semiconductor column;
a first insulating material layer on the first contact material layer;
a gate material layer on the first insulating material layer;
a second insulating material layer on the gate material layer and having an upper surface flush with an upper surface of the gate dielectric material layer; and
a second contact material layer on the upper portion of the semiconductor column,
wherein the first contact material layer covers a portion of the gate dielectric material layer.

10. The semiconductor device of claim 9 , further comprising:
a first contact extending to the first contact material layer;
a second contact extending to the gate material layer; and
a third contact in contact with the second contact material layer.

11. The semiconductor device of claim 10 , wherein the first contact has a first planar surface, the second contact has a second planar surface, and the third contact has a third planar surface, the first, second, and third planar surfaces being formed in a same plane.

12. The semiconductor device of claim 9 , wherein the semiconductor column is a nanowire.

13. The semiconductor device of claim 9 , wherein the semiconductor column comprises an array of semiconductor pillars.

14. The semiconductor device of claim 9 , wherein the semiconductor column comprises silicon.

15. The semiconductor device of claim 9 , wherein the first contact material layer comprises tungsten, nickel, cobalt, titanium, or platinum.

16. The semiconductor device of claim 9 , wherein the second contact material layer comprises tungsten, nickel, cobalt, titanium, or platinum.

Assignees

• Semiconductor Mfg International (Shanghai) Corporation
• Semiconductor Mfg International (Beijing) Corporation

Inventors

• Shen Zhaoxu
• Bei Duohui

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title