Effective device formation for advanced technology nodes with aggressive fin-pitch scaling

Patent metadata

Field	Value
Publication number	US-9564370-B1
Application number	US-201514887538-A
Country	US
Kind code	B1
Filing date	Oct 20, 2015
Priority date	Oct 20, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a gate stack over a portion of each of a plurality of semiconductor fins located on a substrate;
forming a dielectric liner layer over exposed surfaces of the gate stack, the plurality of semiconductor fins and the substrate;
forming a sacrificial dielectric portion filling spaces between the plurality of semiconductor fins;
removing a portion of the dielectric liner layer from an upper portion of the gate stack that is located above the plurality of semiconductor fins to provide a dielectric liner, the dielectric liner laterally surrounding a lower portion of the gate stack that contacts the plurality of the semiconductor fins;
forming a gate spacer laterally surrounding an upper portion of the gate stack that is located above the plurality of the semiconductor fins;
removing the sacrificial dielectric portion; and
removing portions of the dielectric liner that are not covered by the gate spacer from sidewalls of the plurality of semiconductor fins and a top surface of the substrate.

2. The method of claim 1 , wherein the forming the sacrificial dielectric portion comprises:
forming a sacrificial dielectric layer over the dielectric liner layer;
planarizing the sacrificial dielectric layer to expose a topmost surface of the dielectric liner layer located atop the gate stack; and
recessing the sacrificial dielectric layer to provide the sacrificial dielectric portion employing the dielectric liner layer as an etch stop.

3. The method of claim 1 , wherein the forming the gate spacer comprises:
conformally depositing a gate spacer layer on the sacrificial dielectric portion, the dielectric liner, the plurality of semiconductor fins and the upper portion of the gate stack; and
removing horizontal portions of the gate spacer layer by an anisotropic etch.

4. The method of claim 3 , wherein the gate spacer layer has a thickness greater than a thickness of the dielectric liner layer.

5. The method of claim 1 , further comprising forming a source region and a drain region on portions of the semiconductor fins that are not covered by the gate stack, the gate spacer and a remaining portion of the dielectric liner.

6. A method of forming a semiconductor structure comprising:
forming a gate stack over a portion of each of a plurality of semiconductor fins located on a substrate;
forming a sacrificial dielectric portion filling spaces between the plurality of semiconductor fins, the sacrificial dielectric portion laterally surrounding a lower portion of the gate stack;
forming a gate spacer on sidewalls of an upper portion of the gate stack that is not covered by the sacrificial dielectric portion;
removing the sacrificial dielectric portion to expose sidewalls of the lower portion of the gate stack; and
forming a gate liner on the exposed sidewalls of the lower portion of the gate stack.

7. The method of claim 6 , wherein the sacrificial dielectric portion has a top surface coplanar with top surfaces of the plurality of semiconductor fins.

8. The method of claim 6 , wherein the gate spacer has a bottom surface coplanar with top surfaces of the plurality of semiconductor fins.

9. The method of claim 6 , wherein the forming the gate liner on the exposed sidewalls of the lower portion of the gate stack comprises:
forming a dielectric liner layer on exposed surfaces of the plurality of semiconductor fins, the gate spacer, the gate stack and the substrate; and
removing portions of the dielectric liner layer that are not covered by the gate spacer.

10. The method of claim 6 , wherein the gate spacer has a width greater than a width of the gate liner.

Assignees

• IBM

Inventors

• Ok Injo
• Mehta Sanjay C
• Pranatharthiharan Balasubramanian
• Seo Soon-Cheon
• Surisetty Charan V

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H01L21/823462

  Electricity · mapped topic

• H01L21/823468 Primary

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic