Time sensitive networking device

Patent metadata

Field	Value
Publication number	US-10754816-B2
Application number	US-201816230829-A
Country	US
Kind code	B2
Filing date	Dec 21, 2018
Priority date	Dec 21, 2018
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.

First claim

What is claimed is:

1. A device for time sensitive networking, comprising:
a time-sensitive networking controller;
a scheduler of the time-sensitive networking controller;
an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet; and
a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.

2. The device of claim 1 , wherein:
the time-sensitive networking controller comprises a packet buffer; and
the data packet is transmitted from the packet buffer for which the data packet was requested by the scheduler at the pre-fetch time.

3. The device of claim 1 , wherein the enhanced gate control list comprises a plurality of look-up queues, where each of the plurality of look-up queues includes a number of rows in which data packet information is be stored for retrieval by the scheduler.

4. The device of claim 3 , wherein each of the plurality of look-up queues corresponds to a different traffic class where each different traffic class has a differing quality of service.

5. The device of claim 3 , wherein the scheduler compares a front-of-queue data packet in each of the plurality of look-up queues and pre-fetches a queue data packet with a scheduled launch time matching the current time of the scheduler.

6. The device of claim 3 , wherein the scheduler compares a front-of-queue data packet in each of the plurality of look-up queues and pre-fetches a queue data packet where a sum of the scheduled launch time and transmit time of the queue data packet does not conflict with a scheduled launch of a future scheduled data packet.

7. The device of claim 1 , wherein the transmitter of the time-sensitive networking controller is to transmit in a deterministic transmission without making a request through a CPU for an address of the data packet.

8. The device of claim 1 , wherein the time-sensitive networking controller is a networking interface controller.

9. The device of claim 1 , wherein the time-sensitive networking controller applies virtual local area network labels to application requested data packets that are then sorted into a plurality of queues in maintained by the enhanced gate control logic, wherein the virtual local area network labels correspond to the traffic class of the application requested data packets in each of the plurality of queues.

10. The device of claim 1 , wherein the transmitter, enhanced gate control list, and scheduler are all located local to the time-sensitive networking controller and memory accesses using the direct memory access address do not include a query to a CPU.

11. A method for time-sensitive networking, comprising:
generating an enhanced gate control list on a time-sensitive networking controller, the enhanced gate control list comprising a direct memory access address, a launch time, and a pre-fetch time for a data packet; and
transmitting, with a transmitter on the time-sensitive networking controller, the data packet, the data packet retrieved using the direct memory access address at the launch time identified by a scheduler of the time-sensitive networking controller.

12. The method of claim 11 , wherein:
the time-sensitive networking controller comprises a packet buffer; and
the data packet is transmitted from the packet buffer for which the data packet was requested by the scheduler at the pre-fetch time.

13. The method of claim 11 , wherein, wherein the enhanced gate control list comprises a plurality of look-up queues, where each of the plurality of look-up queues includes a number of rows in which data packet information is be stored for retrieval by the scheduler.

14. The method of claim 13 , wherein each of the plurality of look-up queues corresponds to a different traffic class where each different traffic class has a differing quality of service.

15. The method of claim 13 , wherein the scheduler compares a front-of-queue data packet in each of the plurality of look-up queues and pre-fetches a queue data packet with a scheduled launch time matching the current time of the scheduler.

16. The method of claim 13 , wherein the scheduler compares a front-of-queue data packet in each of the plurality of look-up queues and pre-fetches a queue data packet where a sum of the scheduled launch time and transmit time of the queue data packet does not conflict with a scheduled launch of a future scheduled data packet.

17. The method of claim 11 , wherein the transmitter of the time-sensitive networking controller is to transmit in a deterministic transmission without making a request through a CPU for an address of the data packet.

18. The method of claim 11 , wherein the time-sensitive networking controller is a networking interface controller.

19. The method of claim 11 , wherein the time-sensitive networking controller applies virtual local area network labels to application requested data packets that are then sorted into a plurality of queues in maintained by the enhanced gate control logic, wherein the virtual local area network labels correspond to the traffic class of the application requested data packets in each of the plurality of queues.

20. The method of claim 11 , wherein the transmitter, enhanced gate control list, and scheduler are all located local to the time-sensitive networking controller and memory accesses using the direct memory access address do not include a query to a CPU.

21. A system for time sensitive networking, comprising:
a processor;
a main memory;
a time-sensitive networking controller;
a scheduler of the time-sensitive networking controller;
an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address to the main memory, a launch time, and a pre-fetch time for a data packet; and
a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address to the main memory at the launch time identified by the scheduler.

22. The system of claim 21 , wherein:
the time-sensitive networking controller comprises a packet buffer; and
the data packet is transmitted from the packet buffer for which the data packet was requested by the scheduler at the pre-fetch time.

23. The system of claim 21 , wherein the enhanced gate control list comprises a plurality of look-up queues, where each of the plurality of look-up queues includes a number of rows in which data packet information is be stored for retrieval by the scheduler.

24. The system of claim 23 , wherein each of the plurality of look-up queues corresponds to a different traffic class where each different traffic class has a differing quality of service.

25. The system of claim 21 , wherein the transmitter, enhanced gate control list, and scheduler are all located local to the time-sensitive networking controller and memory accesses using the direct memory access address to the main memory are initiated and completed without communication between the time-sensitive networking controller and the processor.

Assignees

• Intel Corp

Inventors

• Kasichainula Kishore

Classifications

• H04L47/564 Primary

  Attaching a deadline to packets, e.g. earliest due date first · CPC title

• H04L47/6215

  Individual queue per QOS, rate or priority · CPC title

• G06F15/17331 Primary

  Distributed shared memory [DSM], e.g. remote direct memory access [RDMA] · CPC title

• H04L12/4645

  Details on frame tagging (routing of packets H04L45/00; support for virtual LAN H04L49/354) · CPC title