Semiconductor device having a multi-layer diffusion barrier

US10749004B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10749004-B2
Application numberUS-201816009925-A
CountryUS
Kind codeB2
Filing dateJun 15, 2018
Priority dateJun 30, 2017
Publication dateAug 18, 2020
Grant dateAug 18, 2020

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a metal layer; an insulating layer disposed above the metal layer; and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer, the multi-layer diffusion barrier comprising: a first material layer including a metallic nitride; a second material layer including a metallic oxide; and at least one intermediate layer disposed between the first material layer and the second material layer, wherein the at least one intermediate layer includes a metal oxynitride. 2. The semiconductor device of claim 1 , wherein the metallic nitride of the first material layer the metallic oxide of the second material layer each include a same metal. 3. The semiconductor device of claim 2 , wherein the metallic oxide of the second material layer is formed by oxidizing the metallic nitride of the first material layer. 4. The semiconductor device of claim 1 , wherein the metallic nitride comprises one of gallium nitride, aluminum nitride, titanium nitride, or tantalum nitride and the metallic oxide comprises one of gallium oxide, aluminum oxide, titanium oxide, or tantalum oxide. 5. The semiconductor device of claim 1 , wherein the metallic oxide of the second material layer has a hexagonal structure. 6. The semiconductor device of claim 1 , wherein the multi-layer diffusion barrier has a thickness of about 10 Å to about 50 Å. 7. The semiconductor device of claim 1 , comprising an etch-stop layer disposed between the multi-layer diffusion barrier and the insulating layer. 8. The semiconductor device of claim 7 , wherein the etch-stop layer comprises a nitrogen doped (silicon) carbide, and oxygen doped (silicon) carbide, or a combination thereof. 9. A semiconductor device, comprising a metal layer; a multi-layer diffusion barrier disposed on the metal layer, the multi-layer diffusion barrier comprising: a first material layer including a metallic nitride; at least one intermediate material layer including a metal oxynitride; and a second material layer including a metallic oxide, wherein the intermediate material layer is disposed between the first material layer and the second material layer; and an etch-stop layer disposed on the multi-layer diffusion barrier; and a low-k layer disposed on the etch-stop layer. 10. The semiconductor device of claim 9 , wherein a metal in each of the metallic nitride, the metal oxynitride, and the metallic oxide include a same metal. 11. The semiconductor device of claim 10 , wherein the intermediate material layer is formed by oxidizing a portion of the first material layer and the second material layer is formed by oxidizing a portion of the intermediate material layer. 12. The semiconductor device of claim 9 , wherein the metallic nitride comprises one of gallium nitride, aluminum nitride, titanium nitride, or tantalum nitride, the metal oxynitride comprises one of gallium oxygen nitride, aluminum oxygen nitride, titanium oxygen nitride, or tantalum oxygen nitride and the metallic oxide comprises one of gallium oxide, aluminum oxide, titanium oxide, or tantalum oxide. 13. The semiconductor device of claim 9 , wherein the metallic oxide of the second material layer has a hexagonal structure. 14. The semiconductor device of claim 9 , wherein the multi-layer diffusion barrier comprises a thickness substantially between 10 Å and 50 Å. 15. The semiconductor device of claim 9 , wherein the etch-stop layer comprises a nitrogen doped (silicon) carbide, and oxygen doped (silicon) carbide, or a combination thereof. 16. A method of forming a semiconductor device, comprising: depositing a conductive metal layer; forming a diffusion barrier on the conductive metal layer, the diffusion barrier comprising a metallic nitride layer deposited on the conductive metal layer, at least one intermediate layer including a metallic oxynitride formed on the metallic nitride layer, and a metallic oxide layer above the metallic oxynitride layer; and depositing an insulating layer above the diffusion barrier. 17. The method of claim 16 , wherein forming the metallic oxide layer comprises oxidizing a portion of the metallic nitride layer. 18. The method of claim 17 , wherein forming the metallic oxide layer comprises forming a metal oxynitride layer prior to forming the metallic oxide layer.

Assignees

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Classifications

  • the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides · CPC title

  • characterised by intermediate layers between substrates and deposited layers · CPC title

  • by contacting with gases, liquids or plasmas · CPC title

  • on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

  • H10W20/075Primary

    of multilayered thin functional dielectric layers · CPC title

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What does patent US10749004B2 cover?
A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/075. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 18 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).