Semiconductor device with plated lead frame

Patent metadata

Field	Value
Publication number	US-10748787-B2
Application number	US-201715794155-A
Country	US
Kind code	B2
Filing date	Oct 26, 2017
Priority date	Feb 26, 2014
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A semiconductor device includes an insulating carrier structure comprised of an insulating inorganic material. The carrier structure has a receptacle in which a semiconductor chip is disposed. The semiconductor chip has a first side, a second side and a lateral rim. The carrier structure laterally surrounds the semiconductor chip and the lateral rim. The semiconductor device also includes a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an insulating carrier structure comprised of an insulating inorganic material, the carrier structure comprising a first planar surface, a second planar surface that is opposite from and parallel to the first planar surface, and a pair of interior sidewalls that face one another and extend between the first and second planar surfaces and form a receptacle;
a semiconductor chip comprising a first side, a second side and a lateral rim, the semiconductor chip being disposed in the receptacle, wherein the carrier structure laterally surrounds the semiconductor chip and the lateral rim; and
a metal structure on and in contact with the second side of the semiconductor chip and embedded in the carrier structure,
wherein the interior sidewalls each comprise:
first sidewall portions that extend from the first planar surface and form a first region of the receptacle that is wider than the semiconductor chip;
second sidewall portions that extend from the second planar surface and form a second region of the receptacle that is narrower than the semiconductor chip; and
a stepped surface that extends from the first sidewall portion to the second sidewall portion and is parallel to the first and second planar surface, and

wherein an outer surface of the metal structure meets both of the second sidewall portions at corner points of the receptacle and is coplanar with the second planar surface of the insulating carrier structure.

2. The semiconductor device of claim 1 , wherein the metal structure has a thickness between about 30 μm to about 500 μm.

3. The semiconductor device of claim 1 , wherein the insulating carrier structure comprises a circumferential groove encompassing a peripheral region of the semiconductor chip.

4. The semiconductor device of claim 1 , wherein the semiconductor chip comprises a semiconductor material comprising a first doping region formed in the semiconductor material at a first side of the semiconductor material and a second doping region formed in the semiconductor material at a second side of the semiconductor material, wherein the first doping region is in electrical connection with a first metallization formed on the first side of the semiconductor material, and wherein the second doping region is in electrical connection with a second metallization formed on the second side of the semiconductor material, wherein the second metallization is covered by and in electrical contact with the metal structure.

5. The semiconductor device of claim 1 , wherein the semiconductor chip comprises a peripheral region in contact with a peripheral stepped region of the receptacle.

6. The semiconductor device of claim 1 , wherein the semiconductor chip is fixed in the receptacle by an adhesive bond.

7. The semiconductor device of claim 1 , wherein the insulating carrier structure comprises a carrier substrate, and wherein the carrier substrate comprises at least one of glass and ceramic.

8. The semiconductor device of claim 7 , wherein the second side face of the semiconductor chip is physically supported by the carrier substrate.

9. The semiconductor device of claim 1 , wherein the receptacle extends through the insulating inorganic material.

10. The semiconductor device of claim 1 , wherein both of the second sidewall portions overlap with the lateral rim of the semiconductor chip.

11. The semiconductor device of claim 10 , wherein the semiconductor chip is completely within the first region and is spaced apart from both of the stepped surfaces, and wherein the metal structure completely fills the second region and completely fills a portion of the first region that is between the semiconductor chip and the stepped surfaces.

12. The semiconductor device of claim 11 , wherein the semiconductor device further comprises adhesive regions that extend from the first planar surface to the metal structure and separate the lateral rim of the semiconductor chip from the first sidewall portions of the insulating carrier structure.

13. The semiconductor device of claim 1 , wherein the semiconductor device further comprises a cover substrate comprised of an insulating inorganic material, the cover substrate comprising a first planar surface, and a second planar surface that is opposite from and parallel to the first planar surface, wherein the second planar surface of the cover substrate faces and is flush against the first planar surface of the carrier structure and the first side of the semiconductor chip.

14. The semiconductor device of claim 13 , wherein the cover substrate comprises an opening that extends from the first planar surface to the second planar surface, and wherein the semiconductor device comprises a further metal structure that fills the opening and contacts the first surface of the semiconductor chip.

15. The semiconductor device of claim 14 , wherein the further metal structure is directly above the semiconductor chip and laterally spaced apart from the lateral rim, and wherein the further metal structure comprises an outer surface that is coplanar with the first planar surface of the cover substrate.

Assignees

• Infineon Technologies Ag

Inventors

• Von Koblinski Carsten
• Fastner Ulrike
• Brockmeier Andre
• Zorn Peter

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title