Program loop control

Patent metadata

Field	Value
Publication number	US-10747536-B2
Application number	US-201716080736-A
Country	US
Kind code	B2
Filing date	Mar 21, 2017
Priority date	Mar 23, 2016
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

A data processing system provides a loop-end instruction for use at the end of a program loop body specifying an address of a beginning instruction of said program loop body. Loop control circuitry ( 1000 ) serves to control repeated execution of the program loop body upon second and subsequent passes through the program loop body using loop control data provided by the loop-end instruction without requiring the loop-end instruction to be explicitly executed upon each pass.

First claim

The invention claimed is:

1. Apparatus for processing data comprising:
processing circuitry to perform processing operations specified by program instructions;
an instruction decoder to decode said program instructions to generate control signals to control said processing circuitry to perform said processing operations; wherein
said instruction decoder comprises loop-end instruction decoding circuitry to decode a loop-end instruction at a finish of a program loop body to generate control signals to control said processing circuitry to store loop control data, to determine if further loop iterations are required and, if further loop iterations are required to branch to a beginning instruction of said program loop body; and further comprising
loop control circuitry to determine, when enabled, if further loop iterations are required, and if further loop iterations are required, to control said processing circuitry to perform processing operations specified by program instructions of said program loop body preceding said loop-end instruction, and excluding said loop-end instruction, under control of said loop control data;
wherein a loop count value is updated each time said program loop body is traversed to perform said processing operations specified by said program loop body, said loop counter value being indicative of the number of loop iterations remaining to be performed;
wherein said loop counter is updated by a number of vector elements that have been processed by said traverse of said program loop body.

2. Apparatus as claimed in claim 1 , comprising a loop control cache to store said loop control data.

3. Apparatus as claimed in claim 1 , comprising a branch predictor and said loop control data is supplied to said branch predictor and said branch predictor uses said loop control data to direct program flow such that processing circuitry performs said processing operations specified by program instructions of said program loop body preceding said loop-end instruction, and excluding said loop-end instruction.

4. Apparatus as claimed in claim 1 , wherein invalidating of said loop control data disables said loop control circuitry such that upon further execution of said program loop, said loop-end instruction is performed again and said loop control data is stored again to re-enable said loop control circuitry.

5. Apparatus as claimed in claim 4 , wherein said loop control data is invalidated upon occurrence of one or more of:
said processing circuitry being reset;
said loop control circuitry or said loop-end instruction determining that no further iterations of said program loop body are required;
an exception being entered;
exception tail-chaining whereby processing proceeds directly from processing a current exception to processing a next exception without restoring state prior to said current exception;
execution of a branch instruction with greater than a predetermined immediate target address range;
returning from an exception;
execution of an instruction that causes an instruction cache of said apparatus to be invalidated;
execution of an instruction that disables caching of said loop control data;
execution of an instruction that disables branch prediction;
execution of a branch-future instruction;
said processing circuitry determining that a branch within said program loop body targets an address that is not between said beginning instruction and said loop-end instruction;
a switch between a secure mode of operation and a non-secure mode of operation; and
one or more implementation defined conditions.

6. Apparatus as claimed in any one of the preceding claim 1 , wherein said loop control data includes one or more of:
loop start data indicative of an address of said beginning instruction;
loop start address offset data that is indicative of the distance between a last instruction of said program loop body that immediately precedes said loop-end instruction and said beginning instruction of said program loop body;
loop end data indicative of an address of a last instruction of said program loop body that immediately precedes said loop-end instruction;
loop remaining instruction data indicative of the number of instructions remaining to be processed before a last instruction of said program loop body that immediately precedes said loop-end instruction is reached;
loop remaining size data indicative of the number of program storage memory locations remaining to be processed before a last instruction of said program loop body that immediately precedes said loop-end instruction is reached; and
loop control valid data.

7. Apparatus as claimed in claim 6 , wherein said loop end data includes a proper subset of bits indicative of a memory storage address of said last instruction starting from a least significance bit end of those bits of said memory storage address that distinguish between starting storage addresses of instructions.

8. Apparatus as claimed in claim 1 , comprising at least one fault syndrome register to store fault syndrome data upon occurrence of faults, wherein said loop control data is stored within said at least one fault syndrome register.

9. Apparatus as claimed in claim 8 , wherein said at least one fault syndrome register has at least one associated valid bit indicating whether any data stored therein is valid fault syndrome data, and said loop control circuitry set said at least one associated valid bit to an invalid state when said at least one fault syndrome register is storing said loop control data.

10. Apparatus as claimed in claim 8 , wherein said at least one fault syndrome register has at least one associated valid bit indicating whether any data stored therein is valid fault syndrome data, wherein if at least one of said at least one associated valid bit is in the valid state said loop-end instruction decoding circuitry does not control said processing circuitry to store said loop control data.

11. Apparatus as claimed in claim 8 , wherein said instruction decoder comprises loop-start instruction decoding circuitry to decode a loop-start instruction preceding said beginning instruction of said program loop body to generate control signals to control said processing circuitry to store a loop count value indicative of a number of times said program loop body is to be executed.

12. Apparatus as claimed in claim 11 , wherein if said loop count value is zero, then performance of processing operations specified by said program loop body is suppressed and processing continues from an instruction following said loop-end instruction.

13. Apparatus as claimed in claim 1 , wherein branching to said beginning instruction control by said loop control circuitry generates trace data corresponding to execution of said loop-end instruction.

14. Apparatus as claimed in claim 1 , wherein the loop control circuitry is configured to control updating of said loop counter in dependence on a control parameter stored in a predetermined state register which is indicative of a number of vector elements to be processed in response to one vector instruction of the program loop body.

15. Apparatus as claimed in claim 1 , wherein said processing circuitry comprises predication loop control circuitry to operate when N ve /N max does not equal a whole number, where N ve is a total number of vector elements to be processed during a number of iterations of the program loop body and N max is a maximum number of vector elements to be processed in response to one vector instruction of the program loop body, to at least partially suppress processing in one or more of said vector processing lan

Assignees

• Advanced Risc Mach Ltd

Inventors

• Grant Alasdair
• Grocutt Thomas Christopher
• Craske Simon John

Classifications

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/381

  Loop buffering · CPC title

• G06F9/324

  using program counter relative addressing · CPC title