Method and apparatus for at-speed scan shift frequency test optimization

Patent metadata

Field	Value
Publication number	US-10746795-B2
Application number	US-201214438234-A
Country	US
Kind code	B2
Filing date	Oct 30, 2012
Priority date	Oct 30, 2012
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

There is provided an integrated circuit comprising at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test, at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state when a sensed supply voltage is below a first predefined value and to output a second logic state when the sensed supply voltage is above the first predefined value, at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test, and control logic operable to gate logic activity including the scan shift operation inside the integrated circuit for a single cycle when the at least one IR drop sensor outputs the first logic state and to allow normal scan test flow when the at least one IR drop sensor outputs the second logic state. There is also provided an associated method of performing at-speed scan testing of an integrated circuit.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
an integrated circuit power supply;
at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test;
at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state in response to a sensed supply voltage being below a first predefined value and to output a second logic state in response to the sensed supply voltage being above the first predefined value, wherein the first predefined value is determined based upon an IR drop indicative of a particular power consumption level during a shift load-in of a scan test data;
at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test; and
control logic operable to gate logic activity of a scan shift operation inside the integrated circuit for a single cycle in response to the at least one IR drop sensor outputs the first logic state, to store incoming data in the at least one memory buffer while the logic activity is gated for the scan shift operation during the single cycle, and to allow normal scan test flow in response to the at least one IR drop sensor outputs the second logic state.

2. The integrated circuit of claim 1 , wherein the control logic is further operable to gate the logic activity within the at least one scan chain under test.

3. The integrated circuit of claim 1 , wherein the IR drop sensor is located in proximity to the at least one scan chain under test or at a location with a highest expected IR drop during load-in of the scan test data into the integrated circuit.

4. The integrated circuit of claim 1 , wherein the IR drop sensor is formed to have a latency value low enough to allow the IR drop sensor to sense an IR drop and provide a logic output in time for the gating of a next shift data load-in cycle decision.

5. The integrated circuit of claim 1 , wherein the memory buffer is a First-In-First-Out buffer.

6. The integrated circuit of claim 1 , wherein the memory buffer is at least one word depth.

7. The integrated circuit of claim 1 , wherein the memory buffer has a depth equal to the test data bus width.

8. The integrated circuit of claim 1 , wherein the memory buffer has a depth equal to at least half the length of a maximum intended length of scan chain, up to the maximum intended length of the scan test chain.

9. The integrated circuit of claim 1 , wherein the memory buffer is operable to hold a next portion of the load-in data when the IR drop sensor outputs the first logic state and to immediately release the next portion of the load-in data in the next cycle when the IR drop sensor outputs the second logic state.

10. The integrated circuit of claim 1 , wherein the memory buffer is further operable to hold a next portion of output test data when the IR drop sensor outputs the first logic state and to immediately release the next portion of the output test data in the next cycle when the IR drop sensor outputs the second logic state.

11. The integrated circuit of claim 1 , wherein the control logic is further operable to provide an output signal indicative of an operational status of the memory buffer to indicate a current status of the at-speed test of the integrated circuit to a test engineer.

12. A method of performing at-speed scan testing of an integrated circuit, comprising:
receiving test data at an input to at least one scan chain under test of an integrated circuit;
measuring a supply voltage with at least one IR drop sensor coupled to the integrated circuit power supply whilst receiving the test data;
outputting a first logic state when a sensed supply voltage is below a first predefined value and outputting a second logic state when the sensed supply voltage is above the first predefined value, wherein the first predefined value is determined based upon an IR drop indicative of a particular power consumption level during a shift load-in of a scan test data;
gating logic activity including a scan shift operation inside the integrated circuit for a single cycle in response to the at least one IR drop sensor outputting the first logic state or allowing normal scan test flow in response to the at least one IR drop sensor outputting the second logic state;
wherein if gating of logic activity occurs, the method further comprises:
storing incoming test data in a memory buffer for at least one test shift cycle while the logic activity of the scan shift operation is gated.

13. The method of claim 12 , further comprising receiving from the memory buffer the stored incoming test data delayed by at least one cycle at an input to at least one scan chain under test.

14. The method of claim 12 , wherein gating logic activity further comprises gating the logic activity within the at least one scan chain under test.

15. The method of claim 12 , further comprising providing the IR drop sensor at a location in proximity to the at least one scan chain under test or at a location with a highest expected IR drop during load-in of the scan test data into the integrated circuit.

16. The method of claim 12 , further comprising storing output test data from the scan chain under test while storing incoming test data.

17. The method of claim 12 , wherein storing incoming test data in a memory buffer for at least one test shift cycle comprises storing incoming test data for an integer multiple of a single test clock cycle.

18. The method of claim 12 , further comprising outputting an output signal indicative of the memory buffer being in use.

Assignees

• Sofer Sergey
• Berkovitz Asher
• Priel Michael
• Nxp Usa Inc

Inventors

• Sofer Sergey
• Berkovitz Asher
• Priel Michael

Classifications

• G01R31/318594 Primary

  Timing aspects (clock circuits G01R31/318552) · CPC title

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

• G01R31/318577

  AC testing, e.g. current testing, burn-in · CPC title

• G01R31/318536

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title

• G01R31/318575

  Power distribution; Power saving · CPC title