PCB based semiconductor device

Patent metadata

Field	Value
Publication number	US-10743404-B2
Application number	US-201916731370-A
Country	US
Kind code	B2
Filing date	Dec 31, 2019
Priority date	Feb 18, 2016
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

A semiconductor device includes a metal base, a transistor die mounted on the metal base, a lid over the transistor die, and a multilayer printed circuit board electrically connected to the transistor die. The multilayer printed circuit board comprises a first portion positioned between the lid and the metal base, a second portion positioned outside of the lid, a plurality of embedded conductive layers, an embedded dielectric layer disposed between at least two of the plurality of embedded conductive layers, and at least one embedded reactive component formed from at least one of the embedded conductive layers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a metal base;
a transistor die mounted on the metal base;
a lid over the transistor die;
a multilayer printed circuit board electrically connected to the transistor die and comprising:
a first portion positioned between the lid and the metal base;
a second portion positioned outside of the lid;
a plurality of embedded conductive layers;
an embedded dielectric layer disposed between at least two of the plurality of embedded conductive layers; and
at least one embedded reactive component formed from at least one of the embedded conductive layers.

2. The semiconductor device of claim 1 , further comprising a Radio Frequency (RF) impedance matching network electrically connected to an RF terminal of the transistor die.

3. The semiconductor device of claim 2 , further comprising a peaking amplifier transistor die mounted on the metal base, wherein:
the transistor die is a main amplifier transistor die;
the RF terminal is an RF input terminal of the main amplifier transistor die; and
the RF impedance matching network is electrically connected to an RF input of the peaking amplifier transistor die.

4. The semiconductor device of claim 2 , further comprising a peaking amplifier transistor die mounted on the metal base, wherein:
the transistor die is a main amplifier transistor die;
the RF terminal is an RF output terminal of the main amplifier transistor die; and
the RF impedance matching network is an output power combiner network electrically connected to an RF output terminal of the peaking amplifier transistor die.

5. The semiconductor device of claim 4 , further comprising:
a further RF impedance matching network electrically connected to an RF input terminal of the main amplifier transistor die and to an RF input terminal of the peaking amplifier transistor die;
wherein the further RF impedance matching network comprises at least one further reactive component formed from at least one of the embedded conductive layers.

6. The semiconductor device of claim 1 , wherein the multilayer printed circuit board further comprises:
a first side attached to the metal base at the first portion;
a second side opposite the first side;
first and second embedded composite fiber layers, each separating an embedded conductive layer from one of the sides;
wherein the embedded dielectric layer has a higher dielectric constant than either of the first and second embedded composite fiber layers.

7. The semiconductor device of claim 6 , wherein the multilayer printed circuit board further comprises:
a first signal layer disposed at the second side;
a first ground layer and a second signal layer, each embedded in the multilayer printed circuit board; and
a second ground layer disposed at the first side.

8. The semiconductor device of claim 7 , wherein:
the first embedded composite fiber layer separates the first signal layer from the first ground layer;
the second embedded composite fiber layer separates the second signal layer from the second ground layer;
wherein the first and second embedded composite fiber layers are each thicker than the embedded dielectric layer.

9. The semiconductor device of claim 7 , wherein:
the at least one embedded reactive component comprises a first capacitor comprising a positive electrode and a ground electrode;
the positive electrode is formed by a first isolated section of the second signal layer; and
the ground electrode is formed by a first isolated section of the first ground layer.

10. The semiconductor device of claim 7 , wherein the at least one embedded reactive component comprises:
a shunt inductance comprising a linear strip of the second signal layer; and
an open-circuit radial stub connected to the shunt inductance and comprising a radially-shaped portion of the second signal layer.

11. The semiconductor device of claim 7 , wherein the multilayer printed circuit board further comprises:
a first via extending through the first embedded composite fiber layer and connected to a first bonding pad formed by an isolated section of the first signal layer;
wherein the at least one embedded reactive component is electrically connected to the first via and comprises an isolated section of the second signal layer.

12. The semiconductor device of claim 11 , further comprising a first set of bond wires directly connected to the first bonding pad and a Radio Frequency (RF) terminal of the transistor die.

13. The semiconductor device of claim 12 , further comprising:
a second bonding pad formed by an isolated portion of the first signal layer; and
a second set of bond wires directly connected to the second bonding pad and a Radio Frequency (RF) terminal of the transistor die;
wherein the first and second sets of bond wires extend in respective directions that are non-parallel to each other.

14. The semiconductor device of claim 7 , further comprising:
a third bonding pad formed by an isolated portion of the first signal layer;
a discrete surface-mount capacitor directly mounted on the third bonding pad; and
wherein the third bonding pad is electrically connected to the at least one embedded reactive component by a second via extending through the first embedded composite fiber layer.

15. The semiconductor device of claim 6 , wherein:
the embedded dielectric layer has a dielectric constant of between 4 and 30; and
each of the first and second embedded composite fiber layers has a dielectric constant of 3.7 or less.

16. The semiconductor device of claim 6 , wherein:
the embedded dielectric layer is formed from a polymer laminate material; and
each of the first and second embedded composite fiber layers is formed from at least one of: FR-1, FR-2, FR-3, FR-4, FR-5, FR-6, G-10, CEM-1, CEM-2, CEM-3, CEM-4, CEM-5.

17. The semiconductor device of claim 6 , wherein:
the embedded dielectric layer has a thickness of between 4 μm and 50 μm; and
each of the first and second embedded composite fiber layers has a thickness of at least 75 μm.

18. The semiconductor device of claim 6 , wherein the first side of the multilayer printed circuit board is configured to attach to a global printed circuit board at the second portion.

19. A semiconductor assembly comprising the semiconductor device and the global printed circuit board of claim 18 .

20. The semiconductor assembly of claim 19 , further comprising a Doherty amplifier comprising the transistor die.

Assignees

• Cree Inc

Inventors

• Mu Qianli
• Gozzi Cristian
• Dani Asmita

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title