Method for forming a stack and stack

US10741799B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10741799-B2
Application numberUS-201716468666-A
CountryUS
Kind codeB2
Filing dateNov 30, 2017
Priority dateDec 12, 2016
Publication dateAug 11, 2020
Grant dateAug 11, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for producing a stack, includes the following steps: forming a first layer able to conduct electricity, forming a layer of interest on the first layer, the layer of interest comprising at least one free volume, forming at least one repairing element, each repairing element at least partially filling a free volume, called the free volume of interest, the repairing element comprising at least one insulating layer and leaving free an upper surface of the layer of interest opposite the first layer located outside of the at least one free volume, forming a second layer, able to conduct electricity, on the layer of interest, the second layer covering the repairing element and the free surface, the step of forming the repairing element comprising the following steps: forming, on the layer of interest, a layer that extends at least partially into the free volume of interest, covering at least one portion of the buffer layer located in the volume of interest with a filling layer, the buffer layer and the filling layer being made from different materials.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for producing a stack, comprising the following steps: forming a first layer able to conduct electricity, forming a layer of interest on the first layer, said layer of interest comprising at least one free volume, forming at least one repairing element, each repairing element at least partially filling a free volume, called the free volume of interest, the repairing element comprising at least one insulating layer and leaving free an upper surface of the layer of interest opposite the first layer and located outside of said at least one free volume, forming a second layer, able to conduct electricity, on the layer of interest, the second layer covering the repairing element and the free surface, the step of forming the repairing element comprising the following steps: forming, on the layer of interest, a buffer layer that extends at least partially into the free volume of interest, covering at least one portion of the buffer layer located in the volume of interest with a filling layer, said buffer layer and the filling layer being made from different materials. 2. The method for producing a stack as claimed in claim 1 , wherein the filling layer penetrates into at least one free volume of interest. 3. The method for producing a stack as claimed in claim 1 wherein the buffer layer prevents any physical contact between the layer of interest and the filling layer. 4. The method for producing a stack as claimed in claim 3 , furthermore comprising a step of removing an excess of the buffer layer and an excess of the filling layer so as to make the free surface of the layer of interest appear and so as to leave a remainder of the buffer layer in the free volume of interest. 5. The process for producing a stack as claimed in claim 4 , wherein the filling layer penetrates into at least one free volume of interest and the removal step is carried out so as to leave a remainder of the filling layer in said free volume of interest, said remainder at least partially covering the remainder of the buffer layer. 6. The process for producing a stack as claimed in claim 1 , wherein the buffer layer is a layer made of insulating material. 7. The process for producing a stack as claimed in claim 1 , wherein the step of forming the buffer layer comprises a step of depositing a layer made of conductive material and a first step of oxidizing the layer made of conductive material. 8. The process for producing a stack as claimed in claim 7 , wherein the step of removing the excess of the buffer layer and of the filling layer is followed by a second step of oxidizing a free surface of the remainder of the buffer layer. 9. The process for producing a stack as claimed in claim 1 , wherein the filling layer is insulating. 10. The process for producing a stack as claimed in claim 1 , wherein the filling layer is able to conduct electricity. 11. The process for producing a stack as claimed in claim 1 , wherein the sum of the thickness of the buffer layer and of the thickness of the filling layer outside of the free volume, in a stacking direction (z) of the stack, is larger than or equal to the nominal thickness e of the layer of interest outside of the free volume. 12. The process for producing a stack as claimed in claim 1 , wherein the buffer layer is an insulating metal oxide. 13. The process for producing a stack as claimed in claim 1 , wherein the filling layer is a resist of SU-8 type or is made of parylene. 14. The process for producing a stack as claimed in claim 1 , wherein the buffer layer is vacuum deposited. 15. The process for producing a stack as claimed in claim 14 , wherein the buffer layer is deposited by atomic layer deposition. 16. The process for producing a stack as claimed in claim 1 , wherein the filling layer is deposited by wet processing. 17. The process for producing a stack as claimed in claim 2 , wherein the removal step comprises the following steps: removing the excess of the filling layer so as to make a free surface of the repairing layer appear, removing the excess of the buffer layer so as to make the free surface of the active layer appear. 18. The process for producing a stack as claimed in claim 17 , wherein the step of removing the excess of the buffer layer comprises a selective removal step allowing the buffer layer to be removed without attacking the layer of interest. 19. The process for producing a stack as claimed in claim 17 , wherein the step of removing the excess of the filling layer comprises a selective removal step allowing the filling layer to be removed without removing the buffer layer. 20. The process for producing a stack as claimed in claim 1 , wherein the free volumes are defects. 21. A stack comprising, in succession: a first layer able to conduct electricity, a layer of interest comprising at least one free volume, a repairing element at least partially filling a free volume, called the free volume of interest, comprising at least one layer made of insulating material and leaving free an upper surface of the layer of interest located outside of said at least one free volume, a second layer, able to conduct electricity covering the repairing element and the upper surface, the repairing element comprising a buffer layer and a filling layer at least partially covering a portion of the buffer layer located in the volume of interest, the buffer layer and the filling layer being made from different materials.

Assignees

Inventors

Classifications

  • Photovoltaic [PV] devices · CPC title

  • Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

  • H10K50/00Primary

    Organic light-emitting devices (integrated devices or assemblies of multiple devices H10K59/00, H10K65/00; organic semiconductor lasers H01S5/36) · CPC title

  • Constructional details · CPC title

  • Constructional details · CPC title

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What does patent US10741799B2 cover?
A method for producing a stack, includes the following steps: forming a first layer able to conduct electricity, forming a layer of interest on the first layer, the layer of interest comprising at least one free volume, forming at least one repairing element, each repairing element at least partially filling a free volume, called the free volume of interest, the repairing element comprising at …
Who is the assignee on this patent?
Commissariat Energie Atomique, Trixell, Commissariat a l'Energie et aux Energies Alternatives
What technology area does this patent fall under?
Primary CPC classification H10K50/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).