Stacked nanowire

Patent metadata

Field	Value
Publication number	US-9252016-B2
Application number	US-201314017822-A
Country	US
Kind code	B2
Filing date	Sep 4, 2013
Priority date	Sep 4, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.

First claim

What is claimed is:

1. A method of fabricating stacked nanowire for a transistor gate, the method comprising:
etching a fin as a vertical structure from a substrate;
forming two or more pairs of spacers at vertically separated first positions of the fin; and
oxidizing vertically separated second positions of the fin, different than the first positions, to form the nanowires at the vertically separated first positions of the fin.

2. The method according to claim 1 , further comprising depositing a hard mask on the substrate prior to the etching the fin, wherein the hardmask is etched with the fin.

3. The method according to claim 1 , wherein the forming the two or more pairs of spacers includes forming each pair of the two or more pairs of spacers on opposite sides of the fin at each of the vertically separated first positions of the fin.

4. The method according to claim 3 , wherein the forming the two or more pairs of the spacers includes forming each pair of the two or more pairs of spacers at each of the vertically separated first positions to be in vertical alignment.

5. The method according to claim 1 , further comprising forming a dielectric film over a first pair of the two or more pairs of spacers.

6. The method according to claim 5 , wherein the forming the two or more pairs of spacers includes forming a second pair of the two or more pairs of spacers on the dielectric film, the vertically separated first positions corresponding with a height of the dielectric film.

7. The method according to claim 5 , wherein the oxidizing leaves the vertically separated first positions of the fin at which the spacers are formed unaffected, the nanowires being formed from the vertically separated first positions of the fins.

8. The method according to claim 7 , further comprising sequentially removing the dielectric film and the two or more spacers.

9. The method according to claim 5 , further comprising removing the dielectric film after the forming the two or more spacers is complete.

10. The method according to claim 9 , wherein the oxidizing leaves the vertically separated first positions of the fin at which the spacers are formed unaffected, the nanowires being formed from the vertically separated positions of the fins.

11. The method according to claim 1 , further comprising forming a gate dielectric around each of the nanowires and forming a transistor gate by enclosing the nanowires in a gate metal.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Doris Bruce B
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title