Semiconductor device having antenna and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10741508-B2
Application number	US-201815965995-A
Country	US
Kind code	B2
Filing date	Apr 30, 2018
Priority date	Apr 30, 2018
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

A semiconductor device including a chip package, a dielectric structure and a first antenna pattern is provided. The dielectric structure disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. A manufacturing method of a semiconductor device is also provided.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor device, comprising:
forming a molding layer on a chip package comprising:
placing a molding chase on the chip package to cover the chip package and then forming a molding material on the chip package; and
removing the molding chase from the chip package to form the molding layer comprising a cavity;

forming a dielectric layer on the molding layer such that a dielectric structure is formed on the chip package, wherein the dielectric structure comprises the cavity and a vent in communication with the cavity; and
forming a first antenna pattern on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

2. The manufacturing method according to claim 1 , wherein the molding chase comprises a concave portion and a convex portion connected to the concave portion,
after placing the molding chase on the chip package, the convex portion of the molding chase is abutted to the chip package, and the concave portion of the molding chase and the chip package form a space for forming the molding material.

3. The manufacturing method according to claim 1 , wherein forming the dielectric layer on the molding layer comprises:
covering the cavity of the molding layer by a dielectric film with a through hole, wherein the through hole of the dielectric film is the vent.

4. The manufacturing method according to claim 1 , wherein the molding chase comprises a release layer, when placing the molding chase on the chip package, the release layer is attached to the chip package.

5. The manufacturing method according to claim 1 , further comprising:
encapsulating a chip by an encapsulant;
forming a redistribution layer on the chip and the encapsulant; and
forming an insulating layer on the redistribution layer to form the chip package.

6. The manufacturing method according to claim 1 , further comprising:
before forming the molding layer, forming a second antenna pattern on an insulating layer of the chip package, wherein after forming the molding layer, the second antenna pattern is inside the cavity.

7. The manufacturing method according to claim 6 , wherein when forming the molding layer on the chip package, the second antenna pattern is covered by a release layer of the molding chase, and after the molding layer is formed, the release layer of the molding chase is removed to expose the second antenna pattern.

8. A manufacturing method of a semiconductor device, comprising:
filling a molding material on a chip package and in a space defined by a molding chase and the chip package;
removing the molding chase to form a molding layer with a cavity;
covering the cavity by a dielectric layer with a through hole to form a dielectric structure comprising the cavity and a vent in communication with the cavity; and
framing a first antenna pattern on the dielectric layer, wherein the first antenna pattern is opposite to the molding layer.

9. The manufacturing method according to claim 8 , wherein the molding chase is provided with a concave portion and a convex portion connected to the concave portion, when filling the molding material, the convex portion of the molding chase is abutted to the chip package, and the molding material is filled in the concave portion.

10. The manufacturing method according to claim 9 , wherein the molding chase comprises a release layer disposed on the convex portion, the manufacturing method further comprises:
placing the molding chase on the chip package such that the release layer on the convex portion is attached to the chip package.

11. The manufacturing method according to claim 8 , further comprising:
before filling the molding material, forming a second antenna pattern on the chip package, wherein after the molding layer is formed, the second antenna pattern is inside the cavity of the molding layer.

12. The manufacturing method according to claim 10 , wherein the molding chase is provided with a release layer, and when filling the molding material, the second antenna pattern is covered by the release layer of the molding chase.

13. A manufacturing method of a semiconductor device, comprising:
forming a molding layer with a cavity on a chip package through a molding chase, wherein the molding layer covers a first portion of a surface of the chip package, and the cavity of the molding layer accessibly exposes a second portion of the surface of the chip package; and
forming a dielectric layer and a first antenna on the molding layer opposite to the chip package, wherein the first antenna and the cavity of the molding layer are formed correspondingly at two opposite surfaces of the dielectric layer.

14. The manufacturing method according to claim 13 , wherein forming the molding layer with the cavity on the chip package through the molding chase comprises:
attaching the molding chase to the second portion of the surface of the chip package;
forming a molding material on the first portion of the surface of the chip package; and
detaching the molding chase from the chip package.

15. The manufacturing method according to claim 14 , wherein the molding chase is provided with a buffer film, and the molding chase is abutted against the second portion of the surface of the chip package through the buffer film.

16. The manufacturing method according to claim 14 , wherein the molding material is laterally injected to fill a gap between a concave portion of the molding chase and the chip package.

17. The manufacturing method according to claim 13 , further comprising:
forming a second antenna on the second portion of the surface of the chip package before forming the molding layer.

18. The manufacturing method according to claim 17 , wherein when forming the molding layer through the molding chase, the second antenna is protected by a buffer film disposed on the molding chase.

19. The manufacturing method according to claim 13 , wherein forming the dielectric layer on the cavity of the molding layer comprises:
providing an outlet for venting the molding layer by forming the dielectric layer with an opening, wherein the opening of the dielectric layer corresponding to the cavity of the molding layer comprises an opening size less than the cavity of the molding layer.

20. The manufacturing method according to claim 13 , further comprising:
encapsulating a chip by an encapsulant;
forming a redistribution layer on the chip and the encapsulant; and
forming an insulating layer on the redistribution layer to form the chip package, wherein after forming the chip package, the molding layer is formed on the insulating layer of the chip package.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wan Albert
• Hsieh Ching-Hua
• Shih Chao-Wen
• Pu Han-Ping
• Chen Meng-Tse
• Chiu Sheng-Hsiang

Classifications

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title