Stochastic computation using pulse-width modulated signals

Patent metadata

Field	Value
Publication number	US-10740686-B2
Application number	US-201815869453-A
Country	US
Kind code	B2
Filing date	Jan 12, 2018
Priority date	Jan 13, 2017
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.

First claim

The invention claimed is:

1. A device comprising:
a stochastic processing unit having a first plurality of inputs,
wherein each input of the first plurality of inputs is configured to receive a respective pulse-width modulated (PWM) signal of a plurality of PWM signals, each of the PWM signals being periodic signals having a respective frequency and period,
wherein each of the PWM signals encodes a respective data value represented by a time duration of a duty cycle relative to the period of the respective PWM signal, and
wherein the stochastic processing unit includes stochastic processing circuitry configured to operate on the plurality of PWM signals and produce a computational result.

2. The device of claim 1 , further comprising PWM generation circuitry configured to generate the plurality of PWM signals by controlling the time duration of the duty cycle of each PWM signal of the plurality of PWM signals to encode the respective data value.

3. The device of claim 2 , wherein the PWM generation circuitry is further configured to generate each PWM signal of the plurality of PWM signals to have different periods.

4. The device of claim 3 , wherein the PWM generation circuitry is further configured to select periods for the plurality of PWM signals such that each of the periods are relatively prime with respect to each other period.

5. The device of claim 3 , wherein, for each PWM signal of the plurality of PWM signals, the PWM generation circuitry is further configured to repeatedly output a full duty cycle representing the respective data value over a stream length.

6. The device of claim 5 , wherein the PWM generation circuitry is further configured to select, for each PWM signal of the plurality of PWM signals, the stream length during which to repeatedly generate and output the full duty cycle of the respective data value based on a least common multiple of the periods selected for all of the plurality of PWM signals.

7. The device of claim 1 , wherein the stochastic processing unit is a first stochastic processing unit, the device further comprising:
a display including a first pixel and a second pixel; and
a second stochastic processing unit, wherein the first stochastic processing unit is positioned beneath the first pixel, and wherein the second stochastic processing unit is positioned beneath the second pixel.

8. The device of claim 1 , wherein the device comprises an integrated circuit, a sensor or an image processor, a video processing circuitry, a camera, or a mobile device.

9. The device of claim 1 , further comprising a sensor device, the sensor device comprising:
a sensing circuit that outputs an analog sense signal indicative of a sensed input;
a ramp generator configured to receive the analog sense signal and output a ramp signal up to an output voltage set as a function of the analog sense signal;
an analog comparator having a first input configured to receive the ramp signal from the ramp generator and a second input configured to receive a reference voltage and configured to output, based on a comparison of the ramp signal and the reference voltage, a first PWM signal of the plurality of PWM signals; and
a clock signal generator outputting a reset clock to reset the analog comparator and control the period for the first PWM signal.

10. The device of claim 9 , wherein the clock signal generator is a first clock signal generator, and wherein the analog comparator is a first analog comparator, the sensor device further comprising:
a second plurality of inputs,
a second comparator configured to output a second PWM signal of the plurality of the PWM signals; and
a second clock signal generator configured to control a period of the second PWM signal,
wherein the first PWM signal encodes a first data value represented by the time duration of the duty cycle of the first PWM signal relative to the time duration of the period of the first PWM signal, and
wherein the second PWM signal encodes a second data value represented by the time duration of the duty cycle of the second PWM signal relative to the time duration of the period of the second PWM signal.

11. The device of claim 10 ,
wherein the first clock signal generator is configured to control the time duration of the duty cycle of the first PWM signal to encode the first data value, and
wherein the second clock signal generator is configured to control the time duration of the duty cycle of the second PWM signal to encode the second data value.

12. The device of claim 11 , wherein the first clock signal generator and the second clock signal generator are further configured to generate the first PWM signal and the second PWM signal to have different periods.

13. The device of claim 11 , wherein the first clock signal generator and the second clock signal generator are further configured to select periods for the first PWM signal and the second PWM signal such that each of the periods are relatively prime with respect to each other period.

14. The device of claim 11 ,
wherein, for the first PWM signal, the first clock signal generator is further configured to repeatedly output a first full duty cycle representing the first data value over a first stream length, and.
wherein, for the second PWM signal, the second clock signal generator is further configured to repeatedly output a second full duty cycle representing the second data value over a second stream length.

15. The device of claim 1 , wherein the stochastic processing circuitry is configured to operate on the plurality of PWM signals by performing a multiplication operation on the plurality of PWM signals to produce the computation result.

16. A method comprising:
generating a plurality of pulse-width modulated (PWM) signals, each PWM signal of the plurality of PWM signals generated to encode a respective data value represented by a time duration of a duty cycle relative to a time duration of a period of the respective PWM signal; and
processing the plurality of PWM signals with stochastic processing circuitry configured to operate on the plurality of PWM signals and produce a computational result.

17. The method of claim 16 , wherein generating the plurality of PWM signals comprises controlling the time duration of the duty cycle of each PWM signal of the plurality of PWM signals to encode the respective data value.

18. The method of claim 16 , wherein generating the plurality of PWM signals comprises generating each PWM signal of the plurality of PWM signals to have different periods.

19. The method of claim 18 , wherein generating the plurality of PWM signals further comprises selecting periods for the plurality of PWM signals such that each of the periods are relatively prime with respect to each other period.

20. The method of claim 18 ,
wherein generating the plurality of PWM signals further comprises repeatedly outputting, for each PWM signal of the plurality of PWM signals, a full duty cycle representing the respective data value over a stream length, and
wherein generating the plurality of PWM signals further comprises selecting, for each PWM signal of the plurality of PWM signals, the stream length during which to repeatedly generate and output the full duty cycle of the respective data value based on a least common multiple of the periods selected for all of the plurality of PWM signals.

Assignees

• Univ Minnesota

Inventors

• Najafi Mohammadhassan
• Jamalizavareh Shiva
• Lilja David J
• Riedel Marcus
• Bazargan Kiarash
• Harjani Ramesh

Classifications

• G06N3/047

  Probabilistic or stochastic networks · CPC title

• G06N7/01 Primary

  Probabilistic graphical models, e.g. probabilistic networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• H03K7/08 Primary

  Duration or width modulation {; Duty cycle modulation} · CPC title

• G06J1/00

  Hybrid computing arrangements · CPC title