Capacitative artificial neural networks

Patent metadata

Field	Value
Publication number	US-10740672-B2
Application number	US-201916371736-A
Country	US
Kind code	B2
Filing date	Apr 1, 2019
Priority date	Mar 30, 2018
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

In one aspect, an apparatus includes a diffusive memristor, and a capacitor integrated in series with the diffusive memristor, wherein the apparatus exhibits volatile memcapacitive behavior. In another aspect, a device includes a transistor, and a memcapacitor integrated onto the gate of the transistor, wherein the memcapacitor exhibits volatile memcapacitive behavior. The memcapacitor includes a diffusive memristor, and a capacitor integrated in series with the diffusive memristor, wherein the gate dielectric of the transistor is replaced with the memcapacitor. In another aspect, an artificial neuron device includes a transistor, a volatile memcapacitor that is configured to operate as an electrically floating gate of the transistor, and one or more synaptic circuits that are coupled to the volatile memcapacitor. The volatile memcapacitor includes a diffusive memristor, and a capacitor integrated in series with the diffusive memristor.

First claim

What is claimed is:

1. An apparatus comprising:
a diffusive memristor; and
a capacitor integrated in series with the diffusive memristor,

wherein the apparatus exhibits volatile memcapacitive behavior.

2. The apparatus of claim 1 , wherein the diffusive memristor is placed on top of the capacitor.

3. The apparatus of claim 1 , wherein the diffusive memristor includes a bottom electrode, a top electrode, a metal-doped dielectric layer between the bottom electrode and the top electrode, and one or more layers of the metal sandwiched between the dielectric layer and at least one of the bottom electrode or the top electrode, and wherein
the bottom electrode includes one of platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), or tungsten (W),
the dielectric layer includes one of a silicon oxide (SiO x ), hafnium oxide (HfO x ), magnesium oxide (MgO x ), aluminum oxide (AlO x ), silicon oxynitride (SiN x O y ), or tantalum oxide (TaO x ),
the metal includes one of silver (Ag), copper (Cu), lithium (Li), sodium (Na), or potassium (K), and
the top electrode includes one of platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), or tungsten (W).

4. The apparatus of claim 1 , wherein the capacitor includes a bottom plate, a top plate, a first dielectric layer and a second dielectric layer, and wherein
the bottom plate includes one of platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), tungsten (W), or aluminum (Al),
the first dielectric layer includes one of tantalum pentoxide (Ta 2 O 5 ), hafnium oxide (HfO x ), or titanium oxide (TiO x ),
the second dielectric layer includes one of a tantalum oxide (TaO x ), hafnium oxide (HfO x ), or titanium oxide (TiO x ), and
the top plate includes one of platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), tungsten (W), or aluminum (Al).

5. The apparatus of claim 4 , wherein the apparatus is configured to control a gate potential of a metal-oxide-semiconductor field-effect transistor (MOSFET).

6. A device comprising:
a transistor; and
a memcapacitor integrated onto the gate of the transistor, wherein the memcapacitor exhibits volatile memcapacitive behavior, the memcapacitor including:
a diffusive memristor; and
a capacitor integrated in series with the diffusive memristor,

wherein a gate dielectric of the transistor is replaced with the capacitor of the memcapacitor.

7. The device of claim 6 , wherein the transistor includes a MOSFET.

8. The device of claim 6 , wherein the diffusive memristor is placed on top of the capacitor.

9. The device of claim 6 , wherein the diffusive memristor includes a bottom electrode, a top electrode, a metal-doped dielectric layer between the bottom electrode and the top electrode, and one or more layers of the metal sandwiched between the dielectric layer and at least one of the bottom electrode or the top electrode, and wherein
the bottom electrode includes one of platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), or tungsten (W),
the dielectric layer includes one of a silicon oxide (SiO x ), hafnium oxide (HfO x ), magnesium oxide (MgO x ), aluminum oxide (AlO x ), silicon oxynitride (SiN x O y ), or tantalum oxide (TaO x ),
the metal includes one of silver (Ag), copper (Cu), lithium (Li), sodium (Na), or potassium (K), and
the top electrode includes one of platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), or tungsten (W).

10. The device of claim 6 , wherein the capacitor includes a bottom plate, a top plate, a first dielectric layer and a second dielectric layer, and wherein
the bottom plate includes one of platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), tungsten (W), or aluminum (Al),
the first dielectric layer includes one of tantalum pentoxide (Ta 2 O 5 ), hafnium oxide (HfO x ), or titanium oxide (TiO x ),
the second dielectric layer includes one of a tantalum oxide (TaO x ), hafnium oxide (HfO x ), or titanium oxide (TiO x ), and
the top plate includes one of platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), palladium (Pd), tungsten (W), or aluminum (Al).

11. An artificial neuron device comprising:
a transistor;
a volatile memcapacitor that is configured to operate as an electrically floating gate of the transistor, the volatile memcapacitor including:
a diffusive memristor; and
a capacitor integrated in series with the diffusive memristor; and

one or more synaptic circuits that are coupled to the volatile memcapacitor.

12. The artificial neuron device of claim 11 , wherein each synaptic circuit includes at least one of a fixed-value capacitor or a reconfigurable capacitor.

13. The artificial neuron device of claim 12 , wherein the fixed-value capacitor has a fixed capacitance value, and
wherein the reconfigurable capacitor has an electrically programmable capacitance value.

14. The artificial neuron device of claim 11 , wherein the transistor includes a MOSFET.

15. The artificial neuron device of claim 11 , wherein the diffusive memristor includes a Pt/Ag/SiO x :Ag/Ag/Pt diffusive memristor.

16. The artificial neuron device of claim 11 , wherein the capacitor includes a Pt/Ta 2 O 5 /TaO x /Pt capacitor.

17. A system comprising:
a first artificial neuron device and a second artificial neuron device, wherein each artificial neuron device includes:
a transistor;
a volatile memcapacitor that is configured to operate as an electrically floating gate of the transistor, the volatile memcapacitor including:
a diffusive memristor; and
a capacitor integrated in series with the diffusive memristor; and

one or more synaptic circuits that are coupled to the volatile memcapacitor, wherein a synaptic circuit includes at least one of a fixed-value capacitor or a reconfigurable capacitor,

wherein a gate voltage of the first artificial neuron device is controlled by a first presynaptic signal, and
wherein a gate voltage of the second artificial neuron device is a weighted sum of a drain voltage of the first artificial neuron device and a second presynaptic signal.

18. The system of claim 17 , wherein the transistor included in the first artificial neuron device is one of an n-MOSFET or a p-MOSFET, and the transistor included in the second artificial neuron device is one of a p-MOSFET or an n-MOSFET.

19. The system of claim 17 , wherein each synaptic circuit includes at least one of a fixed-value capacitor or a reconfigurable capacitor,
wherein the fixed-value capacitor has a fixed capacitance value, and
wherein the reconfigurable capacitor has an electrically programmable capacitance value.

20. The system of claim 17 , wherein the diffusive memristor includes a Pt/Ag/SiO x :Ag/Ag/Pt diffusive memristor, and the capacitor includes a Pt/Ta 2 O 5 /TaO x /Pt capacitor.

Assignees

• Univ Massachusetts
• Univerity Of Massachusetts

Inventors

• Yang Jianhua
• Xia Qiangfei
• Wang Zhongrui
• Wu Qing
• Mclean Mark R

Classifications

• G06N3/065

  Analogue means · CPC title

• G06N3/04 Primary

  Architecture, e.g. interconnection topology · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title