Memory device

Patent metadata

Field	Value
Publication number	US-10424731-B2
Application number	US-201514808584-A
Country	US
Kind code	B2
Filing date	Jul 24, 2015
Priority date	Mar 13, 2015
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

According to one embodiment, a memory device includes a first electrode; a variable resistance layer provided on the first electrode, the variable resistance layer including a chalcogenide compound having a crystal structure; and a second electrode provided on the variable resistance layer. The variable resistance layer includes a first region covering one of an upper surface of the first electrode or a lower surface of the second electrode, and a second region, a concentration of the chemical element being lower in the second region than in the first region.

First claim

What is claimed is:

1. A memory device, comprising:
a first electrode;
a second electrode;
a variable resistance layer provided between the first electrode and the second electrode, the variable resistance layer including a first region and a second region, the first region being in contact with the first electrode, the second region being in contact with the first region and the second electrode, and both of the first region and the second region including a chalcogenide compound having a crystal structure in a first state and a second state and at least one chemical element of germanium, silicon, or carbon, wherein a concentration of the chemical element in the second region is lower than that of the first region in the first state and the second state; and
a control circuit configured to perform a first operation to make the variable resistance layer the first state having a first concentration of the chemical element in the first region, and to perform a second operation to make the variable resistance layer the second state having a second concentration of chemical element in the first region, the first concentration being higher than the second concentration.

2. The memory device according to claim 1 , wherein the chemical element is included inside the crystal structure of the chalcogenide compound.

3. The memory device according to claim 1 , wherein
the chalcogenide compound is a compound of:
at least one type of chemical element selected from a first group and a second group, the first group including germanium, silicon, and carbon, the second group including titanium, vanadium, copper, zinc, chrome, zirconium, platinum, palladium, molybdenum, nickel, manganese, hafnium, bismuth, and antimony; and
at least one type of chemical element selected from a third group including sulfur, selenium, and tellurium.

4. The device according to claim 1 , wherein a concentration of the chemical element is decreased from the first region to the second region.

5. The device according to claim 1 , wherein the chemical element in the first region is aggregated while the variable resistance layer is the first state.

6. The device according to claim 1 , wherein the chemical element has a positively charged state or a cationic state.

7. The device according to claim 1 , wherein the chemical element of the first region is Germanium.

8. The device according to claim 1 , wherein the control circuit is configured to apply a first voltage to the second electrode and decrease the first voltage during a first period in the first operation, to apply a second voltage to the second electrode and decrease the second voltage during a second period longer than the first period in the second operation.

9. The device according to claim 8 , wherein the chemical element is gathered in a lower voltage side.

10. A memory device, comprising:
a variable resistance layer provided between a first electrode and a second electrode, the variable resistance layer including a first region and a second region, the first region being in contact with the first electrode, the second region being in contact with the second electrode and the first region, the variable resistance layer including chalcogenide compound having a crystal structure, the variable resistance layer including at least one chemical element of germanium, silicon, or carbon, wherein a concentration of the chemical element in the second region is lower than that of the first region in a first state and a second state; and
a control circuit configured to perform a first operation to make the variable resistance layer the first state having a first concentration of the chemical element in the first region, the variable resistance layer of the first state being a crystal structure, and to perform a second operation to make the variable resistance layer the second state having a second concentration of chemical element in the first region, the variable resistance layer of the second state being a crystal structure, the first concentration being higher than the second concentration.

11. The device according to claim 10 , wherein a concentration of the chemical element is decreased from the first region to the second region.

12. The device according to claim 10 , wherein the chemical element in the first region is aggregated while the variable resistance layer is the first state.

13. The device according to claim 12 , wherein the chemical element has a positively charged state or a cationic state.

14. The device according to claim 10 , wherein the chemical element of the first region is Germanium.

15. The device according to claim 10 , wherein the control circuit is configured to apply a first voltage to the second electrode and decrease the first voltage during a first period in the first operation, and to apply a second voltage to the second electrode and decrease the second voltage during a second period longer than the first period in the second operation.

16. A memory device, comprising:
a plurality of memory cells, each of which includes a first electrode, a second electrode, and a variable resistance layer being provided between the first electrode and the second electrode, the variable resistance layer including a first region in contact with the first electrode and a second region in contact with the second electrode, the first region being continuous to the second region, both of the first region and the second region including chalcogenide compound having a crystal structure and at least one chemical element of germanium, silicon, or carbon, wherein a concentration of the chemical element in the second region is lower than that of the first region in a first state and a second state;
wherein the plurality of memory cells include at least a first memory cell in the first state representing first data and a second memory cell in the second state representing second data, wherein a first gradient of the chemical element in the first region in the first state is higher than a second gradient of the chemical element in the second region.

17. The device according to claim 16 , wherein the chemical element is Germanium.

18. The device according to claim 16 , wherein the concentration of the chemical element in the first region and the second region decreases as the distance from the first electrode increases.

19. The device according to claim 16 , wherein the first electrode is connected to a bit line extending in a first direction, the second electrode is connected to a word line extending in a second direction different from the first direction, the variable resistance layer being provided between the first electrode and the second electrode in a third direction perpendicular to the first direction and the second direction.

Assignees

• Toshiba Memory Corp

Inventors

• Suzuki Kunifumi
• Yamamoto Kazuhiko

Classifications

• H01L45/1233

  Electricity · mapped topic

• H01L27/2409

  Electricity · mapped topic

• H01L45/126

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic