Manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-10734407-B2
Application number	US-201916448844-A
Country	US
Kind code	B2
Filing date	Jun 21, 2019
Priority date	Aug 19, 2016
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a channel layer;
interlayer insulating layers surrounding the channel layer and stacked to be spaced apart from one another along an extension direction of the channel layer, wherein each of the interlayer insulating layers has a first sidewall facing the channel layer and a second sidewall opposite to the first sidewall;
conductive patterns including main portions and protruding portions extending from the main portions, respectively, the main portions filling interlayer spaces between the insulating layers adjacent to one another, the protruding portions deviating from the interlayer spaces; and
first isolation layers covering the conductive patterns, wherein the conductive patterns are disposed between the first isolation layers and the channel layer,
wherein a distance between the channel layer and each of boundaries, which are defined between the conductive patterns and the first isolation layers at levels of the interlayer spaces, is longer than a distance between the channel layer and the second sidewall of each of the interlayer insulating layers, and
wherein a distance between the protruding portions of the conductive patterns in the extension direction of the channel layer is longer than a distance between the main portions of the conductive patterns in the extension direction of the channel layer,
wherein each of the conductive patterns comprises:
a first conductive pattern filling a portion of each of the interlayer spaces and surrounding the channel layer; and
a second conductive pattern including a first portion contacting the first conductive pattern and filling a remaining portion of each of the interlayer spaces and a second portion extending outwardly to an outside of each of the interlayer spaces from the first portion, and
wherein the second sidewall of each of the interlayer insulating layers further protrudes than a sidewall of the first conductive pattern.

2. The semiconductor device of claim 1 , wherein the conductive patterns have a greater volume than the interlayer spaces.

3. The semiconductor device of claim 1 , wherein the first conductive pattern and the second conductive pattern are formed of substantially the same metal.

4. The semiconductor device of claim 1 , wherein each of the first isolation layers includes a tungsten oxide.

5. The semiconductor device of claim 1 , further comprising a slit defining the second sidewall of each of the interlayer insulating layers.

6. The semiconductor device of claim 5 , wherein the first isolation layers are connected by a second isolation layer formed on the second sidewall of each of the interlayer insulating layers.

7. The semiconductor device of claim 5 , wherein the conductive patterns protrude further toward the slit than the second sidewall of each of the interlayer insulating layers.

8. The semiconductor device of claim 1 , wherein the interlayer spaces filled with the conductive patterns are sealed by the first isolation layers.

9. The semiconductor device of claim 1 , wherein the conductive patterns are electrically separated by the first isolation layers.

10. The semiconductor device of claim 1 , wherein the first isolation layers are arranged to be spaced apart from one another.

Assignees

• Sk Hynix Inc

Inventors

• Park Hae Chan
• Kim Jang Won
• SA Gong Hyun

Classifications

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/042

  the barrier, adhesion or liner layers being seed or nucleation layers · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title