Nonvolatile memory devices comprising a conductive line comprising portions having different profiles and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-10734403-B2
Application number	US-201815991309-A
Country	US
Kind code	B2
Filing date	May 29, 2018
Priority date	Sep 8, 2017
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

Nonvolatile memory devices and methods of fabricating the nonvolatile memory devices are provided. The nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a selection line that is closest to the substrate among the plurality of conductive films. The selection line may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the selection line and a side of the lower portion of the selection line may have different profiles.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a stacked structure comprising a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate; and
a vertical channel structure extending through the stacked structure, wherein the plurality of conductive films comprise a selection line that is closest to the substrate among the plurality of conductive films,
wherein the selection line comprises a lower portion and an upper portion sequentially stacked on the substrate,
wherein a side of the upper portion of the selection line and a side of the lower portion of the selection line have different profiles, and
wherein the vertical channel structure comprises:
a dielectric film on a sidewall of the stacked structure;
a channel film on the dielectric film, the channel film defining a space therein; and
a filling film on the channel film, the filling film filling the space defined by the channel film,
wherein a lower surface of the filling film is closer to an upper surface of the substrate than a lower surface of the selection line.

2. The nonvolatile memory device of claim 1 , wherein the filling film extends on the upper surface of the substrate.

3. The nonvolatile memory device of claim 1 , wherein the selection line directly contacts the channel film.

4. The nonvolatile memory device of claim 1 , wherein the side of the lower portion of the selection line has a first angle with respect to the upper surface of the substrate, and the side of the upper portion of the selection line has a second angle with respect to the upper surface of the substrate, and
wherein the first angle is greater than the second angle.

5. The nonvolatile memory device of claim 1 , wherein the vertical channel structure comprises a first recess contacting the lower portion of the selection line, and
a second recess contacting the upper portion of the selection line, and
wherein a first depth of the first recess is different from a second depth of the second recess.

6. The nonvolatile memory device of claim 5 , wherein the lower portion of the selection line fills the first recess, and the upper portion of the selection line fills the second recess.

7. The nonvolatile memory device of claim 5 , wherein the first depth of the first recess is greater than the second depth of the second recess.

8. The nonvolatile memory device of claim 5 , wherein the vertical channel structure comprises a protrusion between the first recess and the second recess.

9. The nonvolatile memory device of claim 5 , wherein the selection line comprises a concave portion between the upper portion and the lower portion of the selection line.

10. The nonvolatile memory device of claim 1 , wherein a lower surface of the vertical channel structure directly contacts the upper surface of the substrate.

11. A nonvolatile memory device comprising:
a stacked structure comprising a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate; and
a vertical channel structure extending through the stacked structure,
wherein the plurality of conductive films comprise a first conductive film that is closest to the substrate among the plurality of conductive films,
wherein the first conductive film comprises a lower portion and an upper portion sequentially stacked on the substrate,
wherein a side of the upper portion of the first conductive film has a profile different from a profile of a side of the lower portion of the first conductive film, and
wherein the vertical channel structure comprises:
a dielectric film on a sidewall of the stacked structure;
a channel film on the dielectric film, the channel film defining a space therein; and
a filling film on the channel film, the filling film filling the space defined by the channel film,

wherein a lower surface of the filling film is closer to an upper surface of the substrate than a lower surface of the first conductive film.

12. The nonvolatile memory device of claim 11 , wherein the vertical channel structure comprises a first recess contacting the lower portion of the first conductive film, and a second recess contacting the upper portion of the first conductive film, and
wherein a first depth of the first recess is different from a second depth of the second recess.

13. The nonvolatile memory device of claim 12 , wherein the first depth of the first recess is greater than the second depth of the second recess.

14. The nonvolatile memory device of claim 12 , wherein the vertical channel structure comprises a protrusion between the first recess and the second recess.

15. The nonvolatile memory device of claim 11 , wherein the plurality of conductive films further comprise a second conductive film, and
wherein the first conductive film has a first thickness in a vertical direction, the second conductive film has a second thickness in the vertical direction, and the first thickness is greater than the second thickness.

16. A nonvolatile memory device comprising:
a stacked structure comprising a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate; and
a vertical channel structure extending through the stacked structure,
wherein the plurality of conductive films comprise a selection line that is closest to the substrate among the plurality of conductive films,
wherein the selection line comprises a lower portion and an upper portion sequentially stacked on the substrate,
wherein a side of the lower portion of the selection line has a first angle with respect to an upper surface of the substrate, and a side of the upper portion of the selection line has a second angle with respect to the upper surface of the substrate, and
wherein the first angle is greater than the second angle.

17. The nonvolatile memory device of claim 16 , wherein the vertical channel structure comprises:
a dielectric film on a sidewall of the stacked structure;
a channel film on the dielectric film, the channel film defining a space therein; and
a filling film in the space defined by the channel film.

18. The nonvolatile memory device of claim 17 , wherein the filling film directly contacts the upper surface of the substrate.

19. The nonvolatile memory device of claim 18 , wherein the selection line directly contacts the channel film.

20. The nonvolatile memory device of claim 16 , wherein a lower surface of the vertical channel structure directly contacts the upper surface of the substrate.

Assignees

• Eom Taeyong
• Im Jiwoon
• Park Byungsun
• Lim Hyunseok
• Kang Yu Seon
• Kwon Hyukho
• Park Sungjin
• Seo Jiyoun
• Ha Dong Hyeop
• Samsung Electronics Co Ltd

Inventors

• Eom Taeyong
• Im Jiwoon
• Park Byungsun
• Lim Hyunseok
• Kang Yu Seon
• Kwon Hyukho
• Park Sungjin
• Seo Jiyoun
• Ha Dong Hyeop

Classifications

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title