Semiconductor package with multiple molding routing layers and a method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10734247-B2
Application number	US-201715803605-A
Country	US
Kind code	B2
Filing date	Nov 3, 2017
Priority date	Nov 10, 2015
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

First claim

We claim:

1. A method of manufacturing semiconductor devices that each includes a plurality of conductive routing layers, comprising:
obtaining a plated leadframe that includes a plurality of base metal routing circuits and a plurality of package terminals, wherein the plurality of base metal routing circuits forms a base metal plated routing layer;
forming at least one additional metal plated routing layer on top of the base metal plated routing layer, wherein each of the at least one additional metal plated routing layer is formed by:
coupling a plurality of interconnections with routing circuits associated with a previous routing layer that is directly beneath a current metal plated routing layer being formed;
forming an intermediary insulation layer on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer that has a natural surface roughness;
performing an abrasion procedure to roughen at least the top surface of the intermediary insulation layer such that, after the abrasion procedure, the top surface of the intermediary insulation layer has an unnatural surface roughness that is rougher than the natural surface roughness; and
adhering a metal layer on the roughened top surface of the intermediary insulation layer to form a plurality of additional metal routing circuits that is included in the current metal plated routing layer;
coupling a plurality of dies with a topmost metal plated routing layer;

encapsulating the plurality of dies and the topmost metal routing layer with a topmost insulation layer;
etching away exposed copper at the bottom of the leadframe, thereby isolating the plurality of package terminals and exposing the plurality of base metal routing circuits at the bottom of the leadframe;
encapsulating the plurality of exposed base metal routing circuits at the bottom of the leadframe with a bottommost insulation layer; and
performing a cut-through procedure to singulate the semiconductor packages from each other.

2. The method of claim 1 , wherein obtaining a plated leadframe includes:
plating a plurality of areas on surfaces of a copper substrate, thereby resulting in the plated leadframe, wherein the plurality of areas includes bottom plated areas that eventually form the plurality of package terminals and includes top plated areas that form the plurality of base metal routing circuits.

3. The method of claim 2 , wherein the abrasion procedure includes:
coating at least the top surface of the intermediary insulation layer with an adhesion promoter material;
heating the leadframe such that the adhesion promoter material reacts with a portion of the intermediary insulation layer; and
etching away a baked film, resulting in the top surface of the intermediary insulation layer having the unnatural surface roughness that is rougher than the natural surface roughness.

4. The method of claim 3 , wherein each of the at least one additional metal plated routing layer is further formed by, after performing an abrasion procedure and before adhering a metal layer on the roughened top surface:
depositing a catalyst material on the roughened top surface of the intermediary insulation layer; and
removing unwanted areas of the catalyst material such that the remaining areas of the catalyst material form a structure of the plurality of additional metal routing circuits.

5. The method of claim 4 , wherein adhering a metal layer on the roughened top surface includes using a metal chemical solution, wherein metal substance in the metal chemical solution reacts with the remaining areas of the catalyst material such that the adhesion of the metal layer with the intermediary insulation layer having the unnatural surface roughness is better than the adhesion of the metal layer with the intermediary insulation layer having the natural surface roughness.

6. The method of claim 5 , wherein each of the at least one additional metal plated routing layer is further formed by, after adhering a metal layer on the roughened top surface, obtaining a desired thickness of the additional metal routing circuits whereby metal is plated on metal.

7. The method of claim 6 , wherein the desired thickness of the additional metal routing circuits is obtained via an electroless plating process, wherein the electroless plating process includes repeating the depositing step, the removing step and the adhering step in one or more loops.

8. The method of claim 6 , wherein the desired thickness of the additional metal routing circuits is obtained via an electrolytic plating process.

9. The method of claim 6 , wherein each of the at least one additional metal plated routing layer is further formed by, after obtaining a desired thickness of the additional metal routing circuits, removing at least a portion of bus lines.

10. A method of manufacturing semiconductor devices that each includes a plurality of conductive routing layers, comprising:
obtaining a plated leadframe that includes a plurality of base metal routing circuits and a plurality of package terminals, wherein the plurality of base metal routing circuits forms a base metal plated routing layer;
forming at least one additional metal plated routing layer on top of the base metal plated routing layer, wherein each of the at least one additional metal plated routing layer is formed by:
coupling a plurality of interconnections with routing circuits associated with a previous routing layer that is directly beneath a current metal plated routing layer being formed;
forming an intermediary insulation layer on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer that has a natural surface roughness;
performing an abrasion procedure to roughen at least the top surface of the intermediary insulation layer such that, after the abrasion procedure, the top surface of the intermediary insulation layer has an unnatural surface roughness that is rougher than the natural surface roughness;
adhering a metal layer on the roughened top surface of the intermediary insulation layer to form a plurality of additional metal routing circuits that is included in the current metal plated routing layer; and
removing portions of bus lines extending from the plurality of additional metal routing circuits such that the bus lines are not exposed at sides of the semiconductor packages after singulation, wherein the portions are near package singulation paths;

coupling a plurality of dies with a topmost metal plated routing layer;
encapsulating the plurality of dies and the topmost metal routing layer with a topmost insulation layer;
etching away exposed copper at the bottom of the leadframe, thereby isolating the plurality of package terminals and exposing the plurality of base metal routing circuits at the bottom of the leadframe;
encapsulating the plurality of exposed base metal routing circuits at the bottom of the leadframe with a bottommost insulation layer; and
performing a cut-through procedure to singulate the semiconductor packages from each other.

11. The method of claim 10 , wherein the unnatural surface roughness is formed by compound fillers in the intermediary insulation layer protruding beyond compound resin in the intermediary insulation layer.

12. The method of claim 10 , wherein the abrasion procedure includes:
coating at least the top surface of the intermediary insulation layer with an adhesion promoter material;
heating the leadframe such that the adhesion promoter material reacts with a portion of the intermediary insulation layer; and
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Assignees

• Utac Headquarters Pte Ltd

Inventors

• Sirinorakul Saravuth
• Yenrudee Suebphong

Classifications

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/457

  of metallic layers on leadframes · CPC title