Semiconductor device and error management method

Patent metadata

Field	Value
Publication number	US-10733049-B2
Application number	US-201715854191-A
Country	US
Kind code	B2
Filing date	Dec 26, 2017
Priority date	Jun 26, 2017
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

An error management system may be provided. The error management system may include an error analysis unit configured to generate error correction counting values by counting error correction occurrences in a plurality of management blocks and generate permanent error block information for defining whether errors generated in the plurality of management blocks are a permanent error or a temporary error by comparing the error correction counting values and at least one reference value. The error management system may include a block control unit configured to replace an address signal with a new address signal when a management block selected according to the address signal among the plurality of management blocks is previously designated in the permanent error block information.

First claim

What is claimed is:

1. An error management system comprising:
an error analysis unit configured to generate error correction counting values by counting error correction occurrences periodically in a plurality of management blocks, generate a difference value of a previous error correction counting value and a current error correction counting value among the error correction counting values, and generate permanent error block information for defining whether errors generated in the plurality of management blocks are a permanent error or a temporary error by comparing the difference value and the current error correction counting value with at least one reference value; and
a block control unit configured to replace an address signal with a new address signal when a management block selected according to the address signal among the plurality of management blocks is previously designated in the permanent error block information,
wherein the error analysis unit includes:
an error analysis period signal generation unit configured to generate an error analysis period signal according to a read command, active management block information, and a first reference value; and
an error type determination unit configured to generate the permanent error block information according to an error correction occurrence signal, the error analysis period signal, and second and third reference values,

wherein the error type determination unit includes a plurality of error type determination units corresponding to the plurality of management blocks, and
wherein each of the plurality of error type determination units includes:
a counter configured to allow a counting value of the error correction occurrence signal to be shifted to a first register from a plurality of registers when the error analysis period signal is activated;
the plurality of registers configured to sequentially shift an output of the counter according to the error analysis period signal;
a subtractor configured to generate the difference value between outputs of the plurality of registers; and
a comparator configured to generate the permanent error block information by comparing the difference value with second and third reference values, and comparing an output value output from a second register from the plurality of registers with the second and third reference values.

2. The error management system of claim 1 , further comprising a block converter configured to generate active management block information which defines any one of the plurality of management blocks according to the address signal.

3. The error management system of claim 2 , wherein the block converter includes:
a rounding off logic configured to output the address signal by removing a portion of signal bits constituting the address signal; and
a calculation logic configured to calculate which bits of an output of the rounding off logic correspond to which management block among the plurality of management blocks and output a calculation result as the active management block information.

4. The error management system of claim 2 , wherein the block control unit is configured to replace the address signal with the new address signal by comparing the permanent error block information and the active management block information.

5. The error management system of claim 1 , wherein signal bits constituting the error analysis period signal correspond to the plurality of management blocks.

6. The error management system of claim 1 , wherein the error analysis period signal generation unit includes:
a plurality of counters and a plurality of comparators configured in such a manner that one counter and one comparator coupled to the one counter are allocated to a corresponding one of the plurality of management blocks; and
a selection unit configured to provide the read command to a counter of the plurality of counters which is allocated to a management block defined by the active management block information,
wherein each of the plurality of comparators are configured to activate a signal bit corresponding to the management block to which the comparator is allocated among signal bits of the error analysis period signal when a counting value output from a counter coupled to the comparator is equal to or larger than the first reference value.

7. The error management system of claim 1 , wherein the block control unit includes:
a detection unit configured to generate a permanent error flag by comparing active management block information and the permanent error block information; and
a block prohibition unit configured to block use of a management block corresponding to the active management block information by replacing the address signal with the new address signal based on the permanent error flag being activated.

8. A data processing system comprising:
a processor;
a memory system;
a memory controller; and
an error management system, wherein the processor, the memory system, the memory controller, and the error management system are coupled through an input and output (input/output) (I/O) bus,
wherein a memory region of the memory system is divided into a plurality of management blocks and the memory system is configured to generate an error correction occurrence signal whenever error correction through an error correction code circuit occurs, and
the error management system is configured to prohibit use of a management block corresponding to a permanent error by dividing errors generated in the plurality of management blocks into a temporary error and the permanent error by generating a difference value of a previous counting value and a current counting value among counting values and comparing the difference value and the current counting value with at least one reference value, and replacing an address signal which designates a management block corresponding to the permanent error among the plurality of management blocks with a new address,
wherein the counting values are generated by counting the error correction occurrence signal,
wherein the error management system includes:
an error analysis unit configured to generate error correction counting values by counting the error correction occurrence signal in the plurality of management blocks and generate permanent error block information for defining whether the errors generated in the plurality of management blocks are the permanent error or the temporary error by comparing the error correction counting values and at least one reference value; and
a block control unit configured to replace an address signal with a new address signal when a management block selected according to the address signal among a plurality of management blocks is previously designated in a permanent error block information,

wherein the error analysis unit includes:
an error analysis period signal generation unit configured to generate an error analysis period signal according to a read command, active management block information, and a first reference value; and
an error type determination unit configured to generate the permanent error block information according to an error correction occurrence signal, the error analysis period signal, and second and third reference values,

wherein the error type determination unit includes a plurality of error type determination units corresponding to the plurality of management blocks, and
wherein each of the plurality of error type determination units includes:
a counter configured to allow a counting value of the error correction occurrence signal to be shifted to a first register from a plurality of registers when the error analysis period signal is activated;
the plurality of registers configured to sequentially shift an output of th

Assignees

• Sk Hynix Inc

Inventors

• Kim Woongrae

Classifications

• G06F12/0253

  Garbage collection, i.e. reclamation of unreferenced memory · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/76

  using address translation or modifications · CPC title