Integrated circuits with error handling capabilities

Patent metadata

Field	Value
Publication number	US-9575862-B1
Application number	US-201414333408-A
Country	US
Kind code	B1
Filing date	Jul 16, 2014
Priority date	Jan 30, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A logic design may include control and datapath circuitry. The datapath circuitry may be implemented in a double modular redundancy arrangement that generates respective first and second data signals. The control circuitry may be implemented in a triple modular redundancy arrangement. Storage circuitry may be used to buffer the first and second data signals. Real-time error detection circuitry may perform real-time error detection operations on the first and second data signals. Background error checking circuitry may perform background error checking operations such as cyclic redundancy check calculations on configuration data. In response to an error detected by the real-time error detection circuitry, the circuitry may select between the buffered first and second data signals to produce the output data signal. The selection may be performed based on the background error checking operations and may be delayed relative to the real-time detection of the error.

First claim

The invention claimed is:

1. A method of operating circuitry that produces an output data signal, the method comprising:
with first and second circuits, generating first and second respective data signals;
with storage circuitry, buffering the first and second data signals;
with real-time error detection circuitry, performing real-time error detection operations on the first and second data signals;
with background error checking circuitry, performing background error checking operations during normal operation of the first and second circuits; and
in response to an error detected by the real-time error detection circuitry, selecting between the buffered first and second data signals to produce the output data signal based on the background error checking operations.

2. The method defined in claim 1 wherein the first and second circuits comprise first and second datapath circuits, wherein the circuitry comprises programmable logic having programmable elements loaded with configuration data that implements the first and second datapath circuits, and wherein performing the background error checking operations comprises:
continuously performing error-detecting code calculations in validating the configuration data.

3. The method defined in claim 2 wherein the programmable logic comprises programmable regions, wherein the first datapath circuit is implemented using a first set of programmable regions, wherein the second datapath circuit is implemented using a second set of programmable regions, and wherein performing the background error checking operations further comprises:
producing an error location signal that identifies which programmable region the error occurred at.

4. The method defined in claim 3 further comprising:
based on the error location signal, determining whether the error occurred at the first set of programmable regions that implements the first datapath circuit or whether the error occurred at the second set of programmable regions that implements the second datapath circuit;
in response to determining that the error occurred at the first set of programmable regions that implements the first datapath circuit, producing the buffered second data signal as the output data signal; and
in response to determining that the error occurred at the second set of programmable regions that implements the second datapath circuit, producing the buffered first data signal as the output data signal.

5. The method defined in claim 4 wherein a third set of the programmable regions is configured to implement control circuitry in a triple modular redundancy configuration that controls the first and second datapath circuits, the method further comprising:
based on the error location signal, determining whether the error occurred at the third set of the programmable regions that implements the control circuitry; and
in response to determining that the error occurred at the third set of the programmable regions that implements the control circuitry, ignoring the error.

6. The method defined in claim 5 further comprising:
in response to determining that the error did not occur at the first, second, or third set of the programmable regions, loading correct configuration data in the programmable elements and resetting the circuitry.

7. The method defined in claim 2 wherein the background error checking circuitry asserts a CRC error signal in response to identifying the error during background error checking operations, the method further comprising:
with the real-time error detection circuitry, monitoring the CRC error signal during a window of time initialized when the error is detected.

8. The method defined in claim 7 further comprising:
with the real-time error detection circuitry, determining whether the error is a transient error or a permanent error at the end of the window of time.

9. The method defined in claim 8 further comprising:
with the real-time error detection circuitry, enabling a counter to begin incrementing a counter value in response to detecting the error, wherein determining whether the error is a transient error or a permanent error at the end of the window of time comprises:
with the real-time error detection circuitry, identifying the error as a transient error at the end of the window of time if the counter value is less than a threshold.

10. The method defined in claim 9 further comprising:
with the real-time error detection circuitry, identifying the error as a permanent error at the end of the window of time if the counter value is greater than a threshold.

11. The method defined in claim 2 wherein performing the error-detecting code validations comprises calculating cyclic redundancy checks on the configuration data.

12. The method defined in claim 1 further comprising:
in response to detecting the error, gating the first and second circuits until completion of selecting between the buffered first and second data signals to produce the output data signal.

13. The method defined in claim 1 further comprising:
in response to identifying an error by the background error checking operations without any errors detected by the real-time error detection circuitry, ignoring the error.

14. Circuitry, comprising:
first and second circuits that produce respective first and second data signals;
background error checking circuitry that performs background error checking operations on the circuitry; and
real-time error detection circuitry that detects errors based on the first and second data signals and determines the locations of the errors based on the background error checking operations.

15. The circuitry defined in claim 14 wherein the first and second circuits are assigned to a first circuitry class having a first error sensitivity level and wherein the first and second circuits form a double modular redundancy arrangement, the circuitry further comprising:
third, fourth, and fifth circuits assigned to a second circuitry class having a second error sensitivity level that is greater than the first error sensitivity level, wherein the third, fourth, and fifth circuits form a triple modular redundancy arrangement.

16. The circuitry defined in claim 14 further comprising:
buffer circuitry that buffers that first and second data signals, wherein the real-time error detection selects an output signal for the circuitry from the first and second buffered data signals based on the detected errors and the determined locations of the errors.

17. The circuitry defined in claim 16 wherein the circuitry comprises programmable logic regions having programmable elements, wherein a first set of the programmable logic regions is configured to implement the first circuit, and wherein a second set of the programmable logic regions is configured to implement the second circuit.

18. The circuitry defined in claim 17 wherein the first and second circuits comprise first and second datapath circuits, the circuitry further comprising:
first, second, and third control circuits that produce respective first, second, and third control signals; and
a voting circuit that receives the first, second, and third control signals and produces at least one output control signal for the first and second datapath circuits.

19. The circuitry defined in claim 18 wherein the background error checking circuitry calculates cyclic redundancy checks on configuration data stored in the programmable elements to identify errors and produces an error location signal identifying the location of an identified error.

Assignees

• Altera Corp

Inventors

• Hutton Michael David
• Westergreen Dalon L

Classifications

• G06F11/186

  Passive fault masking when reading multiple copies of the same data · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F11/1666

  where the redundant component is memory or memory area · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title