Semiconductor chip having a mask layer with openings

US10727052B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10727052-B2
Application numberUS-201916240142-A
CountryUS
Kind codeB2
Filing dateJan 4, 2019
Priority dateSep 29, 2014
Publication dateJul 28, 2020
Grant dateJul 28, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor chip is disclosed. In an embodiment a semiconductor chip includes a multiply-connected mask layer comprising openings, the openings completely penetrate the mask layer and a semiconductor layer sequence, which, at least in places, is in direct contact with the mask layer, wherein the semiconductor layer sequence is disposed on the mask layer, wherein the mask layer comprises a light-transmissive material, and wherein the light-transmissive material comprises an optical refractive index for light which is smaller than a refractive index of the semiconductor layer sequence.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor chip comprising: a multiply-connected mask layer comprising openings, the openings completely penetrate the mask layer; and a semiconductor layer sequence, which, at least in places is in direct contact with the mask layer, wherein the semiconductor layer sequence is disposed on the mask layer, wherein the mask layer comprises a light-transmissive material, and wherein the light-transmissive material comprises an optical refractive index for light which is smaller than a refractive index of the semiconductor layer sequence; wherein the semiconductor layer sequence includes an active region configured to generate light, and wherein light generated in the active region impinges, at least partially, on the mask layer. 2. The semiconductor chip according to claim 1 , wherein the mask layer includes four or more openings. 3. The semiconductor chip according to claim 1 , further comprising a growth substrate having a growth surface, wherein the growth surface comprises sapphire, and wherein the mask layer is arranged between the growth surface and the semiconductor layer sequence. 4. The semiconductor chip according to claim 3 , wherein the semiconductor layer sequence is in regions of the openings, at least in places in direct contact with the growth surface of the growth substrate. 5. The semiconductor chip according to claim 4 , wherein the optical refractive index of the light-transmissive material of the mask layer is smaller than a refractive index of the growth substrate. 6. The semiconductor chip according to claim 4 , wherein the mask layer is partially removed and hollow spaces are arranged between the semiconductor layer sequence and the growth substrate in the places where the mask layer had previously been arranged. 7. The semiconductor chip according to claim 6 , wherein the hollow spaces are filled with gas. 8. The semiconductor chip according to claim 1 , wherein the mask layer is partially removed. 9. The semiconductor chip according to claim 1 , wherein the mask layer contains a silicon oxide. 10. The semiconductor chip according to claim 1 , wherein a distance between nearest openings is between at least 0.5 μm and at most 15 μm for at least some openings. 11. The semiconductor chip according to claim 1 , wherein the openings are arranged at lattice points of a regular lattice. 12. The semiconductor chip according to claim 1 , wherein a maximum lateral opening dimension is between at least 0.6 μm and at most 2.0 μm for at least some of the openings. 13. The semiconductor chip according to claim 1 , wherein a thickness of the mask layer is between at least 0.2 μm and 10 μm at most. 14. The semiconductor chip according to claim 1 , wherein the semiconductor layer sequence is completely formed over the mask layer.

Assignees

Inventors

Classifications

  • Cutting or separating of wafers, substrates or parts of devices · CPC title

  • Nitrides · CPC title

  • being crystalline insulating materials · CPC title

  • H10P14/271Primary

    characterised by the preparation of substrate for selective deposition · CPC title

  • Bodies · CPC title

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Frequently asked questions

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What does patent US10727052B2 cover?
A semiconductor chip is disclosed. In an embodiment a semiconductor chip includes a multiply-connected mask layer comprising openings, the openings completely penetrate the mask layer and a semiconductor layer sequence, which, at least in places, is in direct contact with the mask layer, wherein the semiconductor layer sequence is disposed on the mask layer, wherein the mask layer comprises a l…
Who is the assignee on this patent?
Osram Oled Gmbh
What technology area does this patent fall under?
Primary CPC classification H10P14/271. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 28 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).