Operation method of memory controller and operation method of storage device

Patent metadata

Field	Value
Publication number	US-10726931-B2
Application number	US-201816023706-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Oct 31, 2017
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A method of operating a memory controller, the memory controller configured to control a nonvolatile memory device, the nonvolatile memory device including a plurality of memory blocks. The method including detecting an invalid block among the plurality of memory blocks; determining an invalid pattern based on a state of the invalid block; and performing an operation on the invalid block such that the invalid block has the invalid pattern.

First claim

What is claimed is:

1. A method of operating a memory controller, the memory controller configured to control a nonvolatile memory device, the nonvolatile memory device including a plurality of memory blocks, the method comprising:
detecting an invalid block among the plurality of memory blocks;
determining an invalid pattern based on a state of the invalid block; and
performing an invalid pattern operation on the invalid block such that the invalid block has the invalid pattern, the invalid pattern operation including at least one of an erase operation, a soft-erase operation, a program operation, a reprogram operation, and a soft-program operation on the invalid block.

2. The method of claim 1 , further comprising:
determining a number of program/erase cycles of the invalid block, and
wherein the determining the invalid pattern,
determines the invalid pattern as a first pattern, in response to the number of program/erase cycles of the invalid block is less than or equal to a first number of times, and
determines the invalid pattern as a second pattern, in response to the number of program/erase cycles of the invalid block being greater than or equal to a second number of times, the second number of times being greater than the first number of times, and the second pattern being different from the first pattern.

3. The method of claim 2 , wherein the invalid pattern operation is performed such that,
threshold voltages of memory cells included in the invalid block are within a range between a first lower limit value and a first upper limit value, in response to determining the invalid pattern as the first pattern, and
threshold voltages of the memory cells included in the invalid block are within a range between a second lower limit value and a second upper limit value, in response to determining the invalid pattern as the second pattern, the second lower limit value and the second upper limit value being greater than the first lower limit value and the first upper limit value, respectively.

4. The method of claim 2 , wherein the invalid pattern operation is performed such that,
a middle value of threshold voltages of memory cells included in the invalid block is a first value, in response to determining the invalid pattern as the first pattern, and
a middle value of threshold voltages of the memory cells included in the invalid block is a second value greater than the first value, in response to determining the invalid pattern as the second pattern.

5. The method of claim 1 , wherein the determining of the invalid pattern based on the state of the invalid block comprises:
performing a cell-counting operation on memory cells of the invalid block based on at least one counting voltage; and
determining the invalid pattern based on a result of the cell-counting operation.

6. The method of claim 1 , wherein the determining of the invalid pattern based on the state of the invalid block comprises:
detecting an error in data from the invalid block; and
determining the invalid pattern based on the error.

7. The method of claim 1 , wherein the determining of the invalid pattern determines the invalid pattern based on a block characteristic table, the block characteristic table including pattern information corresponding to each of word lines of the invalid block.

8. The method of claim 7 , wherein the invalid pattern operation is performed such that,
memory cells connected with a first word line among the word lines of the invalid block have a first pattern, and
memory cells connected with a second word line among the word lines of the invalid block have a second pattern, the second pattern being different from the first pattern, the first word line and the second word line being at different heights from a substrate.

9. The method of claim 8 , wherein
threshold voltages of the memory cells connected with the first word line are within a range between a first lower limit value and a first upper limit value,
threshold voltages of the memory cells connected with the second word line are within a range between a second lower limit value and a second upper limit value, the second lower limit value and the second upper limit value being smaller than the first lower limit value and the first upper limit value, respectively.

10. The method of claim 1 , further comprising:
determining a holding time based on the state of the invalid block; and
using the invalid block as a free block after the holding time elapses from a time point when the invalid block is detected.

11. The method of claim 1 , wherein each of the memory blocks includes a plurality of cell strings, each of the cell strings including a plurality of cell transistors stacked in a direction perpendicular to a substrate.

12. The method of claim 11 , wherein each of the plurality of cell transistors includes a charge-trap flash memory cell.

13. A method of operating a storage device, the storage device including a plurality of memory blocks, the method comprising:
detecting an invalid block among the plurality of memory blocks;
determining an invalid pattern based on a state of the invalid block; and
performing an invalid pattern operation on the invalid block such that the invalid block has the invalid pattern, the invalid pattern operation being at least one of an erase operation, a soft-erase operation, a program operation, a reprogram operation, and a soft-program operation on the invalid block.

14. The method of claim 13 , wherein the invalid block is generated by a garbage collection operation or a read reclaim operation.

15. The method of claim 13 , wherein the invalid pattern operation is performed such that a middle value of threshold voltages of memory cells of the invalid block having the invalid pattern increases as a number of program/erase cycles of the invalid block increases.

16. The method of claim 13 , wherein the invalid pattern operation is performed such that memory cells included in the invalid block having the invalid pattern have a threshold voltage distribution that varies with a height of a word line.

17. The method of claim 13 , further comprising:
determining a holding time based on the state of the invalid block; and
after the holding time elapses in a state where the invalid block has the invalid pattern,
erasing the invalid block, and
programming valid data in the invalid block that is erased.

18. A method of operating a memory controller, the memory controller configured to control a nonvolatile memory device that includes a plurality of memory blocks, the method comprising:
detecting an invalid block among the plurality of memory blocks;
determining an invalid pattern based on a state of the invalid block; and
sending an invalid pattern command to the nonvolatile memory device, the invalid pattern command including an address for the invalid block, the invalid pattern command corresponding to at least one of an erase operation, a soft-erase operation, a program operation, a reprogram operation, and a soft-program operation on the invalid block.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Raeyoung
• Kim Hyunjung
• Lee Sung-Bok
• Gwak Soyeong
• Nam Sang-Wan

Classifications

• G11C16/349 Primary

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0617 Primary

  in relation to availability · CPC title