Operating method for nonvolatile memory and operating method for storage device including the nonvolatile memory

Patent metadata

Field	Value
Publication number	US-9646704-B2
Application number	US-201514800038-A
Country	US
Kind code	B2
Filing date	Jul 15, 2015
Priority date	Nov 7, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

An operation method of a storage device including a nonvolatile memory and a memory controller controlling the nonvolatile memory, includes transmitting a multi-program command to the nonvolatile memory by the memory controller; and programming memory cells connected to two or more word lines by the nonvolatile memory in response to the multi-program command.

First claim

What is claimed is:

1. An operation method of a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory, the operation method comprising:
transmitting a single multi-program command to the nonvolatile memory from the memory controller;
programming memory cells connected to two or more word lines of a memory block in the nonvolatile memory to close the memory block responsive to the single multi-program command;
transmitting a program command to the nonvolatile memory from the memory controller; and
programming memory cells connected to a word line in the nonvolatile memory to store data responsive to the program command.

2. The operation method of claim 1 , further comprising:
selecting a memory block of the nonvolatile memory to be closed; and
determining whether memory cells connected to two or more word lines of the selected memory block are in an erase state,
wherein said transmitting the single multi-program command comprises transmitting the single multi-program command corresponding to the selected memory block responsive to determination that the memory cells connected to the two or more word lines of the selected memory block are in the erase state.

3. The operation method of claim 1 , further comprising:
determining whether an external device connected to the storage device has entered a power-off process; and
determining whether a memory block of the nonvolatile memory is an open memory block,
wherein said transmitting the single multi-program command comprises transmitting the single multi-program command to program word lines connected to memory cells of the open memory block that are in an erase state, responsive to determination of entry into the power-off process.

4. The operation method of claim 1 , further comprising:
detecting restoration of the storage device from a sudden power off state; and
determining whether a memory block of the nonvolatile memory is an open memory block,
wherein said transmitting the single multi-program command comprises transmitting the single multi-program command to program word lines connected to memory cells of the open memory block that are in an erase state, responsive to detection of the restoration from the sudden power off state.

5. The operation method of claim 1 , further comprising:
receiving an erase request from an external host connected to the storage device;
erasing a memory block of the nonvolatile memory responsive to the erase request; and
determining whether a write request to the erased memory block is scheduled,
wherein said transmitting the single multi-program command comprises transmitting the single multi-program command to program the erased memory block, responsive to determination that the write request is not scheduled.

6. The operation method of claim 1 , wherein the two or more word lines are programmed at a same time.

7. The operation method of claim 1 , wherein memory cells of the nonvolatile memory are connected to bit lines and word lines including the two or more word lines, and
wherein said programming the memory cells comprises:
biasing the bit lines to a voltage based on dummy data;
applying a pass voltage to the word lines; and
applying a program voltage to the two or more word lines.

8. The operation method of claim 7 , wherein said programming memory cells further comprises:
biasing the bit lines to a power supply voltage;
applying a verification voltage to the two or more word lines; and
applying a read voltage to the word lines other than the two or more word lines.

9. The operation method of claim 1 , wherein the memory cells connected to the two or more word lines are programmed to have a threshold voltage distribution range greater than a threshold voltage distribution range of an erase state.

10. The operation method of claim 1 , wherein said programming the memory cells comprises:
programming memory cells connected to a first word line among the two or more word lines to have a first threshold voltage distribution range greater than a threshold voltage distribution range of an erase state; and
programming memory cells connected to a second word line among the two or more word lines to have a second threshold voltage distribution range higher than the first threshold voltage distribution range.

11. The operation method of claim 10 , wherein among the first and second word lines, the second word line is located closer to remaining ones of the word lines other than the first and second word lines.

12. The operation method of claim 1 , wherein said programming the memory cells comprises programming using dummy data without receiving data from the memory controller.

13. The operation method of claim 1 , wherein said programming of the memory cells comprises programming the memory cells repeatedly a predetermined number of times without verification of the memory cells.

14. An operation method of a nonvolatile memory comprising:
receiving a single multi-program command at the nonvolatile memory;
programming memory cells connected to two or more word lines of a memory block in the nonvolatile memory using dummy data to close the memory block responsive to the single multi-program command;
receiving a program command at the nonvolatile memory; and
programming other memory cells connected to a word line in the nonvolatile memory to store data responsive to the program command.

15. The operation method of claim 14 , wherein the memory cells are simultaneously programmed using the dummy data.

16. A storage device comprising:
a nonvolatile memory comprising a plurality of memory blocks; and
a memory controller configured to select a memory block to be closed from among the memory blocks of the nonvolatile memory, the selected memory block including memory cells that are connected to two or more word lines and that are in an erase state, the memory controller further configured to transmit a single multi-program command with information of the selected memory block,
wherein the nonvolatile memory is configured to program the memory cells of the selected memory block connected to the two or more word lines using dummy data to close the selected memory block, responsive to the single multi-program command;
wherein the memory controller selects another memory block and transmits a program command with information of the selected another memory block, and
wherein the nonvolatile memory programs other memory cells of the selected another memory block connected to a word line to store data responsive to the program command.

17. The storage device of claim 16 , wherein the memory controller is further configured to determine whether an external device connected to the storage device has entered a power-off process, to determine whether a memory block from among the memory blocks is an open memory block, and to transmit the single multi-program command with information of the open memory block responsive to determination of entry into the power-off process,
wherein the nonvolatile memory is further configured to program memory cells that are connected to two or more word lines of the open memory block and that are in an erase state using the dummy data, responsive to the single multi-program command.

18. The storage device of claim 16 , wherein the memory controller is further configured to detect restoration of the storage device from a sudden power off state, to determine whether a memory block from among the memory blocks is an open memory block, and to transmit the sin

Assignees

• Moon Sangkwon
• Bae Sung-Hwan
• Ro Seungkyung
• Samsung Electronics Co Ltd

Inventors

• Moon Sangkwon
• Bae Sung-Hwan
• Ro Seungkyung

Classifications

• H01L27/115

  Electricity · mapped topic

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title