Chip on film and display device including the same

Patent metadata

Field	Value
Publication number	US-10726787-B2
Application number	US-201816213907-A
Country	US
Kind code	B2
Filing date	Dec 7, 2018
Priority date	Dec 15, 2017
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

A chip on film and a display device including the same selectively outputs gate transmission signals and data outputs to reduce the number of output pads in a data driving IC. The COF includes first to third groups of data input pads, gate input pads, and output pads. A data driving IC includes first to third groups of output buffers, a first switchable output unit configured to selectively supply gate transmission signals and an output of the first group of output buffers to the first group of output pads, and a second switchable output unit configured to selectively supply the gate transmission signals and an output of the third group of output buffers to the third group of output pads. An output of the second group of output buffers is supplied to the second group of output pads between the first and the third groups of output pads.

First claim

What is claimed is:

1. A chip on film comprising:
data input pads and gate input pads that are connected to a data driving integrated circuit (IC) and arranged in a first pad region of a circuit film; and
first to third groups of output pads that are connected to the data driving IC and arranged in a second pad region of the circuit film,
wherein the data driving IC comprises:
first to third groups of output buffers,
a first switchable output unit configured to selectively supply a plurality of gate transmission signals received from the gate input pads and an output of the first group of output buffers to the first group of output pads, and
a second switchable output unit configured to selectively supply the plurality of gate transmission signals and an output of the third group of output buffers to the third group of output pads; and
wherein an output of the second group of output buffers is supplied to the second group of output pads arranged between the first group of output pads and the third group of output pads,
wherein the first switchable output unit comprises a first group of multiplexers (MUXs) configured to select the plurality of gate transmission signals or select the output of the first group of output buffers in response to an enable signal and to supply the selected signals or the output of the first group of output buffers to the first group of output pads; and
wherein the second switchable output unit comprises a second group of MUXs configured to select the plurality of gate transmission signals or select the output of the third group of output buffers in response to a reverse enable signal obtained by inverting the enable signal and to output the selected signals or the output of the third group of output buffers to the third group of output pads.

2. The chip on film of claim 1 , wherein, when the first switchable output unit selects the plurality of gate transmission signals and supplies the selected signals to the first group of output pads, the second switchable output unit selects the output of the third group of output buffers, and the second group of the output buffers and the third group of the output buffers output data through the output pads of the second group and the third group respectively or, when the second switchable output unit selects the plurality of gate transmission signals and supplies the selected signals to the third group of output pads, the first switchable output unit selects the output of the first group of output buffers, and the first group of output buffers and the second group of output buffers output data through the first group of output pads and the second group of output pads respectively.

3. The chip on film of claim 1 , wherein the data driving IC comprises:
first to third groups of digital/analog converters (DACs) connected to the first to third groups of output buffers for respective channels;
first to third groups of latches connected to the first to third groups of DACs for respective channels; and
a shift register comprising first to third groups of stages connected to the first to third groups of latches for respective channels to supply a sampling signal; and
wherein the shift register further comprises:
a first demultiplexer (DEMUX) configured to supply a latch start pulse to a first stage of the first group of stages or a first stage of the second group of stages in response to the enable signal; and
a second DEMUX configured to output a sampling signal of a last stage of the second group of stages to a next-end data driving IC as a carry output or supply the sampling signal to a first stage of the third group of stages in response to the reverse enable signal.

4. The chip on film of claim 3 , wherein, when the first switchable output unit supplies the plurality of gate transmission signals to the first group of output pads, the second group of stages and the third group of stages perform a shift operation according to control of the first and the second DEMUXs to latch pixel data to the second group of latches and the third group of latches and to supply the latched pixel data to the second group of output pads and the third group of output pads through the second group of DACs and the third group of DACs and the second group of output buffers and the third group of output buffers respectively.

5. The chip on film of claim 3 , wherein, when the second switchable output unit supplies the plurality of gate transmission signals to the third group of output pads, the first group of stages and the second group of stages perform a shift operation according to control of the first and the second DEMUXs to latch pixel data to the first and the second groups of latches and to supply the latched pixel data to the first and the second groups of output pads through the first and the second groups of DACs and the first and the second groups of the output buffers respectively.

6. The chip on film of claim 1 , wherein the gate input pads comprise at least one group of a first group of gate input pads positioned outside one side of the data input pads and a second group of gate input pads positioned outside another side of the data input pads; and
wherein the first switchable output unit is connected to the first group of gate input pads and the second switchable output unit is connected to the second group of gate input pads or the first and the second switchable output units are commonly connected to any one group of the first group of gate input pads and the second group of gate input pads through an input terminal of the data driving IC.

7. A display device comprising:
a panel comprising a pixel array;
first and second gate drivers connected to opposite sides of the panel to drive gate lines of the pixel array; and
a plurality of chips on film in which a plurality of data driving ICs for driving data lines of the pixel array are respectively installed on a plurality of circuit films and which are connected between the panel and a printed circuit board (PCB),
wherein a first chip on film connected to the first gate driver of the plurality of chips on film and a second chip on film connected to the second gate driver transmit a plurality of gate transmission signals,
wherein the first chip on film and the second chip on film each includes:
data input pads and gate input pads that are connected to any one of the data driving ICs and arranged in a first pad region of a circuit film; and
first to third groups of output pads that are connected to the any one data driving IC and arranged in a second pad region of the circuit film,
wherein the any one data driving IC comprises first to third groups of output buffers, a first switchable output unit configured to selectively supply the plurality of gate transmission signals received from the gate input pads and an output of the first group of output buffers to the first group of output pads, and a second switchable output unit configured to selectively supply the plurality of gate transmission signal and an output of the third group of output buffers to the third group of output pads; and
wherein an output of the second group of output buffers is supplied to the second group of output pads arranged between the first group of output pads and the third group of output pads,
wherein the first switchable output unit comprises a first group of multiplexers (MUXs) configured to select the plurality of gate transmission signals or select the output of the first group of output buffers in response to an enable signal and to supply the selected signals or the output of the first group of output buffers to the first group of output pads; and
wherein the second switchable output unit comprises a second group of MUXs configured to select the plurality of gate transmission

Assignees

• Lg Display Co Ltd

Inventors

• Cho Soon-Dong
• Han Jae-Won
• Hur Jun-O
• Kim Dong-Ju

Classifications

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2300/0828

  forming a digital to analog [D/A] conversion circuit · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G02F1/133

  Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) · CPC title