Display device having ESD circuit

Patent metadata

Field	Value
Publication number	US-9633589-B2
Application number	US-201514608657-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	Jul 21, 2014
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A display device includes a first interconnection line, a first data driver, a second interconnection line, an electrostatic discharge (ESD) circuit, and a display panel. The first connection line transmits a data driving signal. The first data driver includes the first interconnection line and output a data signal based on the data driving signal. The second interconnection line passes through the first data driver and transmits a gate driving signal. The ESD) circuit in the first data driver and discharges static electricity transmitted through the second interconnection line. The first gate driver outputs a gate signal based on the gate driving signal transmitted through the second interconnection line. The display panel receives the data signal and the gate signal.

First claim

What is claimed is:

1. A display device, comprising:
a first interconnection line to transmit a data driving signal, the first interconnection line including first group interconnection lines and second group interconnection lines, the data driving signal including first group data driving signals and second group data driving signals;
a first data driver chip including first data terminals to receive the first group data driving signals, the first data driver chip to output first group data signals based on the first group data driving signals;
a second interconnection line passing through the first data driver chip, the second interconnection line to transmit a gate driving signal;
an electrostatic discharge (ESD) circuit in the first data driver chip, the ESD circuit to discharge static electricity transmitted through the second interconnection line;
a first gate driver to output a gate signal based on the gate driving signal transmitted through the second interconnection line;
a second data driver chip, through which the second interconnection line does not physically pass, including second data terminals to receive the second group data driving signals and to output second group data signals based on the second group data driving signals; and
a display panel to receive the data signal and the gate signal, wherein:
when the first data driver chip and the second data driver chip have a same size, gaps between the first data terminals of the first data driver chip are different from those of the second data terminals of the second data driver chip, and
when the first data driver chip and the second data driver chip have different sizes, the gaps between the first data terminals of the first data driver chip are same as those of the second data terminals of the second data driver chip.

2. The device as claimed in claim 1 , wherein the second interconnection line is connected to an input terminal of the ESD circuit.

3. The device as claimed in claim 2 , wherein the ESD circuit includes one or more switches.

4. The device as claimed in claim 3 , wherein the switches include diodes.

5. The device as claimed in claim 4 , wherein the ESD circuit includes:
a first diode electrically connected between the input terminal of the ESD circuit and a third interconnection line applied with a logic voltage; and
a second diode electrically connected between the input terminal of the ESD circuit and a fourth interconnection line applied with a ground voltage.

6. The device as claimed in claim 5 , wherein:
the first diode includes a cathode terminal connected to the third interconnection line and an anode terminal connected to the input terminal of the ESD circuit, and
the second diode includes an anode terminal connected to the fourth interconnection line and a cathode terminal connected to the input terminal of the ESD circuit.

7. The device as claimed in claim 6 , when negative static electricity is transmitted to the ESD circuit through the second interconnection line, the negative static electricity is discharged to the fourth interconnection line through the second diode.

8. The device as claimed in claim 6 , wherein the ESD circuit includes:
a power clamp connected in parallel to the first and second diodes between the third and fourth interconnection lines.

9. The device as claimed in claim 8 , when positive static electricity is transmitted to the ESD circuit through the second interconnection line, the positive static electricity is discharged to the fourth interconnection line through the first diode, the third interconnection line, and the power clamp.

10. The device as claimed in claim 1 , wherein:
the first data driver chip includes a first terminal to receive the gate driving signal from a timing controller and a second terminal to output the gate driving signal to the first gate driver, and
the second interconnection line includes a first interconnection portion to connect the timing controller to the first terminal, a second interconnection portion to connect the first terminal to the second terminal, and a third interconnection portion to connect the second terminal to the first gate driver.

11. The device as claimed in claim 10 , wherein the second interconnection portion of the second interconnection line is electrically connected to an input terminal of the ESD circuit.

12. The device as claimed in claim 1 , wherein:
the second data driver chip includes a plurality of second data driver chips, and
the second interconnection line does not physically pass through the plurality of second data driver chips.

13. The device as claimed in claim 12 , wherein the first data driver chip is adjacent to an outermost one of the plurality of second data driver chips.

14. The device as claimed in claim 1 , further comprising:
a second gate driver in the display panel and spaced apart from the first gate driver.

15. The device as claimed in claim 14 , wherein the first data driver chip includes at least two first data driver chips,
the at least two first data driver chips corresponding to the first and second gate drivers, respectively.

16. The device as claimed in claim 15 , wherein the at least two first data driver chips are respectively disposed at positions corresponding to the first and second gate drivers.

17. The device as claimed in claim 1 , wherein:
the first gate driver is integrated on the display panel, and the first and second data chips are mounted on a flexible circuit board, the flexible circuit board being integrated on the display panel.

18. The device as claimed in claim 1 , wherein the gate driving signal includes a vertical trigger signal, a first clock signal, and a second clock signal.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Sujin
• Ban Young-Il
• Kang Sun-Koo
• Son Sunkyu

Classifications

• G09G2300/08

  Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements · CPC title

• G09G2330/04

  Display protection · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3685

  Details of drivers for data electrodes · CPC title

• H01L27/0266

  Electricity · mapped topic