Network interface device and method

Patent metadata

Field	Value
Publication number	US-10721072-B2
Application number	US-201715721619-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Sep 29, 2017
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

A network interface device comprises an integrated circuit device comprises at least one processor. A network interface device comprises a memory. The integrated device is configured to execute a function with respect to at least a part of stored data in said memory.

First claim

The invention claimed is:

1. A network interface device comprising:
an integrated circuit device comprising at least one processor;
a memory configured to store computer code instructions comprising operations performable by the at least one processor, wherein said integrated circuit device is configured to:
execute a function in dependence upon at least part of the computer code that is stored in said memory; and
cause transmission of a result of the execution of the function over a network,
wherein the result is such that a size of said result together with a size of said stored at least part of the computer code is greater than a size of available memory which stores said at least part of the computer code.

2. A network interface device as claimed in claim 1 , wherein said memory comprises at least one of a first memory in said integrated circuit device and a second memory external to said integrated circuit device, wherein said stored computer code is stored in one or more of said first memory and second memory.

3. A network interface device as claimed in claim 1 , wherein said function comprises a hash function calculated over the at least part of the computer code.

4. A network interface device as claimed in claim 1 , wherein the result of said function is such that said function is calculated by said at least one processor over the stored computer code.

5. A network interface device as claimed in claim 1 , wherein the result of said function is dependent on content of at least a part of stored data stored in said memory.

6. A network interface device as claimed in claim 1 , wherein said integrated circuit device is configured to receive information identifying a location of said at least part of the computer code and use said information to execute said function with respect to said computer code instructions at said location.

7. A network interface device as claimed in claim 6 , wherein said information identifying a location comprises index information.

8. A network interface device as claimed in claim 1 , wherein said integrated circuit device is configured to output the result of said function.

9. A network interface device as claimed in claim 2 , comprising, in said integrated circuit device, a data store configured to store a first encryption key, said at least one processor is configured to encrypt data to be stored in said second memory using said first encryption key.

10. A network interface device as claimed in claim 9 , wherein said data store is provided by said first memory.

11. A network interface device as claimed in claim 9 , wherein said data store is a fuse data store.

12. A network interface device as claimed in claim 9 , wherein said integrated circuit device is such that debug access is unavailable.

13. A network interface device as claimed in claim 9 , wherein integrated circuit device is such that at least some computer code executing on said at least one processor is unable to directly read said first encryption key.

14. A network interface device as claimed in claim 1 , wherein said integrated circuit device comprises at least one of an ASIC, an FPGA, an integrated circuit and an integrated circuit die.

15. A network interface device as claimed in claim 9 , wherein a second key is provided in said network interface device, said second key being a private key associated with said network interface device.

16. A network interface device as claimed in claim 15 , wherein said second key is stored in one of said data store, the first memory and the second memory.

17. A network interface device as claimed in claim 15 , wherein said network interface device is configured to receive a nonce, the integrated circuit device is configured to encrypt the nonce with said second key and output said encrypted nonce.

18. A method comprising:
executing a function in dependence upon at least part of the computer code that is stored in said memory; and
cause transmission of the result of the execution of the function over a network,
performing by at least one processor of the integrated circuit device operations of the computer code instructions,
wherein said stored data is stored in one or more of memory external to an integrated circuit device and memory on said integrated circuit device,
wherein the result is such that a size of said result together with a size of said stored at least part of the computer code is greater than a size of available memory which stores said at least part of the computer code.

19. A method as claimed in claim 18 , wherein said function comprises a hash function calculated over the at least part of the computer code.

20. A method as claimed in claim 18 , wherein an output of said function is dependent on the content of said at least a part of said stored data.

21. A method as claimed in claim 18 , comprising receiving information identifying a location of stored data and using said information when execute said function with respect to said stored at least part of the computer code at said location.

22. A method as claimed in claim 21 , wherein said information identifying a location comprises index information.

23. A method as claimed in claim 18 , comprising outputting a result of said function.

24. A device comprising:
a network interface device, said network interface device comprising:
an integrated circuit device comprising at least one processor and a first memory; and
a second memory external to said integrated circuit device, wherein said integrated circuit device is configured to execute a function in dependence upon at least part of computer code that is stored in one or more of said first memory and said second memory,
wherein said integrated circuit device is configured to output a result of the execution of the function,
wherein the computer code instructions comprise operations performable by the at least one processor,
wherein the result is such that a size of said result together with a size of said stored at least part of the computer code is greater than a size of available memory which stores said at least part of the computer code.

25. A device as claimed in claim 24 , wherein said function comprises a hash function calculated over the at least part of the computer code.

26. A device as claimed in claim 24 , wherein the result of said function has a size greater than a size of available memory for storing the at least part of the computer code data.

27. A device as claimed in claim 24 , wherein the result of said function is dependent on the content of said at least a part of stored data stored in one or more of said first memory and said second memory.

28. A device as claimed in claim 24 , wherein said integrated circuit device is configured to receive information identifying a location of the at least part of the computer code and use said information to execute said function with respect to the at least part of the computer code stored at said location, wherein said device is configured to provide said information.

29. A device as claimed in claim 26 , wherein said information identifying a location comprises index information.

30. A device as claimed in claim 27 , wherein said device is configured to compare said received result with an expected result.

Assignees

• Xilinx Inc

Inventors

• Pope Steven L
• Riddoch David J
• Fox Paul

Classifications

• G06F21/51 Primary

  at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/572

  Secure firmware programming, e.g. of basic input output system [BIOS] · CPC title

• H04L9/3236 Primary

  using cryptographic hash functions · CPC title

• H04L9/0894

  Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage · CPC title