Method for manufacturing resistivity standard sample and method for measuring resistivity of epitaxial wafer

Patent metadata

Field	Value
Publication number	US-10720366-B2
Application number	US-201716324435-A
Country	US
Kind code	B2
Filing date	Jul 28, 2017
Priority date	Aug 25, 2016
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

A method for manufacturing a resistivity standard sample include the steps, preparing a first-conductivity-type silicon single crystal substrate, measuring a thickness of the silicon single crystal substrate by using a thickness measuring instrument having traceability to the national standard, growing a second-conductivity-type silicon epitaxial layer on the silicon single crystal substrate to fabricate an epitaxial wafer having a p-n junction, measuring a thickness of the epitaxial wafer by using the thickness measuring instrument having the traceability to the national standard, obtaining a thickness of the silicon epitaxial layer from the thicknesses of the epitaxial wafer and the silicon single crystal substrate, and measuring a resistivity of the silicon epitaxial layer by using a resistivity measuring instrument having traceability to a resistivity standard reference material. Consequently, the method for manufacturing which enables manufacturing a resistivity standard sample having the traceability to the resistivity standard reference material of, e.g., NIST is provided.

First claim

The invention claimed is:

1. A method for manufacturing a resistivity standard sample comprising:
a step of preparing a first-conductivity-type silicon single crystal substrate;
a substrate thickness measuring step of measuring a thickness of the first-conductivity-type silicon single crystal substrate by using a thickness measuring instrument calibrated by a standard block gauge having traceability to a national standard;
a vapor phase growth step of growing a second-conductivity-type silicon epitaxial layer having a second conductivity type which is a conductivity type opposite to the first conductivity type on the first-conductivity-type silicon single crystal substrate to fabricate an epitaxial wafer having a p-n junction;
an epitaxial wafer thickness measuring step of measuring a thickness of the epitaxial wafer by using the thickness measuring instrument;
a step of obtaining a thickness of the second-conductivity-type silicon epitaxial layer from the thickness of the epitaxial wafer and the thickness of the first-conductivity-type silicon single crystal substrate; and
a resistivity measuring step of measuring a resistivity of the silicon epitaxial layer by using a resistivity measuring instrument having traceability to a resistivity standard reference material,
wherein the resistivity standard reference material is at least one of NIST standard reference materials SRM 2541 to SRM 2547.

2. The method for manufacturing a resistivity standard sample according to claim 1 ,
wherein impurity concentration in the first-conductivity-type silicon single crystal substrate is set to be less than 1×10 18 atoms/cm 3 .

3. The method for manufacturing a resistivity standard sample according to claim 2 ,
wherein the thickness of the second-conductivity-type silicon epitaxial layer is set to 100 μm or more and 200 μm or less.

4. A method for measuring a resistivity of an epitaxial wafer comprising calibrating a C-V method measuring device which is a front surface electrode by using a resistivity standard sample fabricated by the method for manufacturing a resistivity standard sample according to claim 2 as a secondary standard sample, and measuring an epitaxial layer resistivity of an epitaxial wafer as a measurement target by the calibrated C-V method measuring device which is the front surface electrode.

5. A method for measuring a resistivity of an epitaxial wafer comprising measuring an epitaxial layer resistivity of a P/P-type or N/N-type silicon epitaxial wafer to provide a tertiary standard sample by using a C-V method measuring device which is a front surface electrode calibrated with a resistivity standard sample fabricated by the method for manufacturing a resistivity standard sample according to claim 2 as a secondary standard sample, calibrating a C-V method measuring device which is a back surface electrode by using the tertiary standard sample, and measuring an epitaxial layer resistivity of an epitaxial wafer as a measurement target by the calibrated C-V method measuring device which is the back surface electrode.

6. The method for manufacturing a resistivity standard sample according to claim 1 ,
wherein the thickness of the second-conductivity-type silicon epitaxial layer is set to 100 μm or more and 200 μm or less.

7. A method for measuring a resistivity of an epitaxial wafer comprising calibrating a C-V method measuring device which is a front surface electrode by using a resistivity standard sample fabricated by the method for manufacturing a resistivity standard sample according to claim 6 as a secondary standard sample, and measuring an epitaxial layer resistivity of an epitaxial wafer as a measurement target by the calibrated C-V method measuring device which is the front surface electrode.

8. A method for measuring a resistivity of an epitaxial wafer comprising measuring an epitaxial layer resistivity of a P/P-type or N/N-type silicon epitaxial wafer to provide a tertiary standard sample by using a C-V method measuring device which is a front surface electrode calibrated with a resistivity standard sample fabricated by the method for manufacturing a resistivity standard sample according to claim 6 as a secondary standard sample, calibrating a C-V method measuring device which is a back surface electrode by using the tertiary standard sample, and measuring an epitaxial layer resistivity of an epitaxial wafer as a measurement target by the calibrated C-V method measuring device which is the back surface electrode.

9. A method for measuring a resistivity of an epitaxial wafer comprising calibrating a C-V method measuring device which is a front surface electrode by using a resistivity standard sample fabricated by the method for manufacturing a resistivity standard sample according to claim 1 as a secondary standard sample, and measuring an epitaxial layer resistivity of an epitaxial wafer as a measurement target by the calibrated C-V method measuring device which is the front surface electrode.

10. A method for measuring a resistivity of an epitaxial wafer comprising measuring an epitaxial layer resistivity of a P/P-type or N/N-type silicon epitaxial wafer to provide a tertiary standard sample by using a C-V method measuring device which is a front surface electrode calibrated with a resistivity standard sample fabricated by the method for manufacturing a resistivity standard sample according to claim 1 as a secondary standard sample, calibrating a C-V method measuring device which is a back surface electrode by using the tertiary standard sample, and measuring an epitaxial layer resistivity of an epitaxial wafer as a measurement target by the calibrated C-V method measuring device which is the back surface electrode.

Assignees

• Shinetsu Handotai Kk

Inventors

• Kume Fumitaka

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/20

  of semiconductor materials · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• Y02P70/50

  Manufacturing or production processes characterised by the final manufactured product · CPC title