Programmable unit for metadata processing

Patent metadata

Field	Value
Publication number	US-10719630-B2
Application number	US-201816134942-A
Country	US
Kind code	B2
Filing date	Sep 18, 2018
Priority date	Nov 19, 2014
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

A system and method for metadata processing that can be used to encode an arbitrary number of security policies for code running on a stored-program processor. This disclosure adds metadata to every word in the system and adds a metadata processing unit that works in parallel with data flow to enforce an arbitrary set of policies, such that metadata is unbounded and software programmable to be applicable to a wide range of metadata processing policies. This instant disclosure is applicable to a wide range of uses including safety, security, and synchronization.

First claim

The invention claimed is:

1. A Reduced Instruction Set Computer (RISC), comprising:
a pipeline processor including a plurality of stages, wherein the stages further comprise a fetch stage, a decode stage, an execute stage, a memory stage, and a writeback stage; and
a metadata processing stage as one of the stages of the pipeline processor between the memory stage and the writeback stage, the metadata processing stage defining one or more security policies on data flowing within the pipeline processor and adding metadata tags to the data to generate metadata tagged data that is moved through the stages.

2. The Reduced Instruction Set Computer according to claim 1 , further comprising at least one cache coupled to at least one of the decode stage, the execute stage, the memory stage, and the writeback stage.

3. The Reduced Instruction Set Computer according to claim 1 , further comprising a rule cache lookup stage.

4. The Reduced Instruction Set Computer according to claim 1 , wherein the metadata tags are unbounded to enforce any number of policies at the same time.

5. The Reduced Instruction Set Computer according to claim 1 , further comprising: at least one microarchitecture optimization operatively connected with the metadata processing stage, wherein the microarchitecture optimization is selected from a group comprising grouped instruction operation codes, tag compression, tag translation, and miss handler acceleration.

6. The Reduced Instruction Set Computer according to claim 5 , further comprising a tag compression logic utilizing a spatial tag locality to compress tag bits, and after compression transfer the compressed tag bits to and from an off-chip memory.

7. The Reduced Instruction Set Computer according to claim 5 , further comprising a tag translation logic to translate the tag bits between different levels of memory hierarchy.

8. The Reduced Instruction Set Computer according to claim 5 , further comprising a plurality of tag checking and propagation rules defined in software and executable by the processor; and a metadata processing rule cache operating in parallel with the stage of the pipeline processor.

9. The Reduced Instruction Set Computer according to claim 1 , wherein the metadata processing stage is a Programmable Unit for Metadata Processing (PUMP) having logic adapted to provide policy enforcement and metadata propagation.

10. The Reduced Instruction Set Computer according to claim 9 , wherein the logic of the PUMP includes instructions to empirically evaluate runtime, energy, power ceiling, and area impacts of the PUMP.

11. The Reduced Instruction Set Computer according to claim 9 , wherein the logic of the PUMP includes instructions to implement a set of micro-architectural optimizations.

12. The Reduced Instruction Set Computer according to claim 11 , wherein the logic of the PUMP includes instructions to measure gains from the set of micro-architectural optimizations.

13. The Reduced Instruction Set Computer according to claim 9 , wherein the PUMP includes hardware for single-cycle common-case computation on metadata.

14. The Reduced Instruction Set Computer according to claim 9 , wherein the PUMP includes instructions for two output tags to be computed from up to five input tags.

15. The Reduced Instruction Set Computer according to claim 9 , wherein the PUMP includes a hardware cache of the most recently used rules.

16. The Reduced Instruction Set Computer according to claim 1 , wherein the metadata processing stage is a separate stage that is distinct from the memory stage and the writeback stage.

17. A Reduced Instruction Set Computer (RISC), comprising:
a pipeline processor including a plurality of stages, wherein the stages further comprise a fetch stage, a decode stage, an execute stage, a memory stage, and a writeback stage; and
a metadata processing stage as one of the stages of the pipeline processor between the execute stage and the writeback stage, the metadata processing stage defining one or more security policies on data flowing within the pipeline processor and adding metadata tags to the data to generate metadata tagged data that is moved through the stages.

18. A Reduced Instruction Set Computer (RISC), comprising:
a pipeline processor including a plurality of stages, wherein the stages further comprise a fetch stage, a decode stage, an execute stage, a memory stage, and a writeback stage; and
a metadata processing stage as one of the stages of the pipeline processor between the decode stage and the writeback stage, the metadata processing stage defining one or more security policies on data flowing within the pipeline processor and adding metadata tags to the data to generate metadata tagged data that is moved through the stages.

Assignees

• Bae Sys Inf & Elect Sys Integ
• Univ Pennsylvania

Inventors

• Chiricescu Silviu S
• Dehon Andre
• Dhawan Udit

Classifications

• G06F21/71 Primary

  to assure secure computing or processing of information · CPC title

• G06F21/64 Primary

  Protecting data integrity, e.g. using checksums, certificates or signatures · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/45

  Caching of specific data in cache memory · CPC title

• G06F2212/1041

  Resource optimization · CPC title