System and method for providing in-storage acceleration (ISA) in data storage devices

Patent metadata

Field	Value
Publication number	US-10719474-B2
Application number	US-201815921400-A
Country	US
Kind code	B2
Filing date	Mar 14, 2018
Priority date	Oct 11, 2017
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

First claim

What is claimed is:

1. A bridge device comprising:
a data storage interface that accesses data stored in a non-transitory data storage medium of a data storage device;
a processor comprising a plurality of processor cores;
a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, reconfigurable interconnects, and memories;
a host interface that receives a host command for configuring the data storage device to run a data acceleration process in the bridge device from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and
a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots, reconfigures at least one or more of the reconfigurable logic blocks and the reconfigurable interconnects included in the AABB slot by loading to the RTL bitstream into the reconfigurable logic blocks and interconnecting the reconfigurable logic blocks via the reconfigurable interconnects, and loads the firmware driver to a processor core of the processor;
wherein the processor core loaded with the firmware driver runs the data acceleration process of the remote application by accessing the data stored in the non-transitory data storage medium of the data storage device via the data storage interface and processing the local data using the at least one or more of the reconfigurable logic blocks and the reconfigurable interconnects that are reconfigured by the configuration controller.

2. The bridge device of claim 1 , wherein the data storage interface is an NVMe interface.

3. The bridge device of claim 1 , wherein the host interface is an Ethernet interface, and the data storage device is an NVMe-oF SSD.

4. The bridge device of claim 1 , wherein the remote host computer sends a second RTL bitstream and a second firmware image to the bridge device, and the configuration controller discards the RTL bitstream downloaded to the AABB slot and downloads the second RTL bitstream and loads the second firmware to the processor core to run a second data acceleration process using the second RTL bitstream and the second firmware.

5. The bridge device of claim 1 , wherein the bridge device further sends discovery information to the remote application, wherein the discovery information includes features, characteristics, and attributes of the AABB slots.

6. The bridge device of claim 1 , wherein the host command includes a management command for enabling, disabling, and discarding the RTL bitstream and the firmware driver.

7. The bridge device of claim 1 , wherein the host command includes an AABB slot communication command to communicate with an active AABB slot, wherein the AABB slot communication command includes an identifier of an active AABB slot.

8. The bridge device of claim 1 , wherein the processor core loaded with the firmware driver accesses the data stored in the non-transitory data storage medium via the data storage interface while running the data acceleration process of the remote application using a set of application program interface (API) calls that are agnostic to the remote application.

9. The bridge device of claim 1 , wherein one or more AABB slots includes a logic area, look-up tables (LUTs), random-access memory (RAM) blocks, hard macros, and clock and reset signals.

10. The bridge device of claim 1 , wherein one or more AABB slots includes a programmable clock/reset, an advanced extensible interface (AXI) to the processor core, a double data rate (DDR) memory interface, a peripheral component interconnect express (PCIe) interface, and an Ethernet interface.

11. A data storage device comprising:
a non-transitory data storage medium;
a processor comprising a plurality of processor cores;
a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, reconfigurable interconnects, and memories;
a host interface that receives a host command for configuring the data storage device to run a data acceleration process in the data storage device from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and
a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots, reconfigures at least one or more of the reconfigurable logic blocks and the reconfigurable interconnects included in the AABB slot by loading to the RTL bitstream into the reconfigurable logic blocks and interconnecting the reconfigurable logic blocks via the reconfigurable interconnects, and loads the firmware driver to a processor core of the processor,
wherein the processor core loaded with the firmware driver runs the data acceleration process of the remote application by accessing and processing local data stored in the non-transitory data storage medium of the data storage device using the at least one or more of the reconfigurable logic blocks and the reconfigurable interconnects that are reconfigured by the configuration controller.

12. The data storage device of claim 11 , wherein the data storage device is a nonvolatile memory express (NVMe) solid-state drive (SSD).

13. The data storage device of claim 11 , wherein the data storage device is an NVMe over fabrics (NVMe-oF) SSD, and the host interface is an Ethernet interface.

14. The data storage device of claim 11 , wherein the remote host computer sends a second RTL bitstream and a second firmware image to the data storage device, and the configuration controller downloads the second RTL bitstream and loads the second firmware to the processor core to run a second data acceleration process using the second RTL bitstream and the second firmware.

15. The data storage device of claim 11 , wherein the data storage device further sends discovery information to the remote application, wherein the discovery information includes features, characteristics, and attributes of the AABB slots.

16. The data storage device of claim 11 , wherein the host command includes a management command for enabling, disabling, and discarding the RTL bitstream and the firmware driver.

17. The data storage device of claim 11 , wherein the host command includes an AABB slot communication command to communicate with an active AABB slot, wherein the AABB slot communication command includes an identifier of an active AABB slot.

18. The data storage device of claim 11 , wherein the processor core loaded with the firmware driver accesses the data stored in the non-transitory data storage medium and runs the data acceleration process of the remote application using a set of application program interface (API) calls that are agnostic to the remote application.

19. The data storage device of claim 11 , wherein one or more AABB slots includes a logic area, look-up tables (LUTs), random-access memory (RAM) blocks, hard macros, and clock and reset signals.

20. The data storage device of claim 11 , wherein one or more AABB slots includes a programmable clock/reset, an advanced extensible interface (AXI) to the processor core, a double data rate (DDR) memory interface, a peripheral component interconnect express (PCIe) interface, and an Ethernet interface.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kachare Ramdas
• WORLEY Fred
• Yao Xuebin

Classifications

• G06F13/1673 Primary

  using buffers · CPC title

• H04L49/9078

  using an external memory or storage device · CPC title

• G06F9/4406 Primary

  Loading of operating system · CPC title

• G06F3/067

  Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title